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soc/intel/skl: set PEG port state to auto 

Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.

Note: Currently, this only works with the AST PCI bridge disabled or the
      VGA jumper set to disabled on coreboot, while it works on vendor
      in any case. The reason for this is still unclear.

Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
      instead of just PC3

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Michael Niewöhner 2020-12-04 14:59:00 +01:00 committed by Patrick Georgi
parent 416b828f47
commit 88e85b3de4
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/skylake/romstage/romstage.c
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@ -173,6 +173,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */ dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
m_cfg->Peg0Enable = dev && dev->enabled; m_cfg->Peg0Enable = dev && dev->enabled;
if (m_cfg->Peg0Enable) { if (m_cfg->Peg0Enable) {
m_cfg->Peg0Enable = 2;
m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
/* Use maximum possible link speed */ /* Use maximum possible link speed */
m_cfg->Peg0MaxLinkSpeed = 0; m_cfg->Peg0MaxLinkSpeed = 0;
@ -186,6 +187,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */ dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
m_cfg->Peg1Enable = dev && dev->enabled; m_cfg->Peg1Enable = dev && dev->enabled;
if (m_cfg->Peg1Enable) { if (m_cfg->Peg1Enable) {
m_cfg->Peg1Enable = 2;
m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
m_cfg->Peg1MaxLinkSpeed = 0; m_cfg->Peg1MaxLinkSpeed = 0;
m_cfg->Peg1PowerDownUnusedLanes = 1; m_cfg->Peg1PowerDownUnusedLanes = 1;
@ -196,6 +198,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */ dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
m_cfg->Peg2Enable = dev && dev->enabled; m_cfg->Peg2Enable = dev && dev->enabled;
if (m_cfg->Peg2Enable) { if (m_cfg->Peg2Enable) {
m_cfg->Peg2Enable = 2;
m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
m_cfg->Peg2MaxLinkSpeed = 0; m_cfg->Peg2MaxLinkSpeed = 0;
m_cfg->Peg2PowerDownUnusedLanes = 1; m_cfg->Peg2PowerDownUnusedLanes = 1;