some progress on kconfig:

- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
  the socket it has, and the CPUs are pulled in automatically. There is
  some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
  - intel/eagleheights
  - intel/jarrell
  - intel/mtarvon
  - intel/truxton
  - intel/xe7501devkit
  - sunw/ultra40
  - supermicro/h8dme
  - tyan/s2850
  - tyan/s2875
  - via/epia
  - via/epia-cn
  - via/epia-m
  - via/epia-m700
  - via/epia-n
  - via/pc2500e
(PPC not considered, probably overlooked something)

All of them only _build_, but some options are probably completely
wrong. To be fixed later

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

Makefile

@@ -145,6 +145,14 @@ subdirs:=$(PLATFORM-y) $(BUILD-y)
 $(eval $(call evaluate_subdirs))
 
 
+define c_dsl_template
+$(obj)/$(1)%.c: src/$(1)%.dsl
+	@printf "    IASL       $$(subst $$(shell pwd)/,,$$(@))\n"
+	iasl -p $$(basename $$@) -tc $$<
+	perl -pi -e 's/AmlCode/AmlCode_$$(notdir $$(basename $$@))/g' $$(basename $$@).hex
+	mv $$(basename $$@).hex $$@
+endef
+
 define objs_c_template
 $(obj)/$(1)%.o: src/$(1)%.c
 	@printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
@@ -195,6 +203,7 @@ endef
 
 usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
 usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
+$(eval $(call usetemplate,c,dsl))
 $(eval $(call usetemplate,objs,c))
 $(eval $(call usetemplate,objs,S))
 $(eval $(call usetemplate,initobjs,c))
@@ -233,7 +242,7 @@ STACKPROTECT += $(call cc-option, -fno-stack-protector,)
 CFLAGS = $(STACKPROTECT) $(INCLUDES) $(MAINBOARD_OPTIONS) -Os -nostdinc
 CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS +=-Wwrite-strings -Wredundant-decls -Wno-trigraphs 
-CFLAGS += -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow 
+CFLAGS += -Wstrict-aliasing -Wshadow 
 CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 
 CBFS_COMPRESS_FLAG:=l

src/cpu/Kconfig

@@ -17,6 +17,10 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x8000 if CPU_INTEL_CORE
 
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0
+
 config SMP
 	bool
 	default y if MAX_CPUS != 1

src/cpu/intel/Kconfig

@@ -1,5 +1,15 @@
+source src/cpu/intel/model_69x/Kconfig
+source src/cpu/intel/model_6dx/Kconfig
 source src/cpu/intel/model_6ex/Kconfig
 source src/cpu/intel/model_6fx/Kconfig
-source src/cpu/intel/socket_mFCPGA478/Kconfig
+source src/cpu/intel/model_1067x/Kconfig
-source src/cpu/intel/socket_PGA370/Kconfig
+
+source src/cpu/intel/bga956/Kconfig
+source src/cpu/intel/ep80579/Kconfig
 source src/cpu/intel/slot_2/Kconfig
+source src/cpu/intel/socket_mFCPGA478/Kconfig
+source src/cpu/intel/socket_mPGA478/Kconfig
+source src/cpu/intel/socket_mPGA479M/Kconfig
+#source src/cpu/intel/socket_mPGA603/Kconfig
+source src/cpu/intel/socket_mPGA604/Kconfig
+source src/cpu/intel/socket_PGA370/Kconfig

src/cpu/intel/Makefile.inc

@@ -3,13 +3,15 @@
 #
 # Therefore: ONLY include Makefile.inc from socket directories!
 
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956
+subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
 
-#socket_mPGA478
-#socket_mPGA479M
-#socket_mPGA603
-#socket_mPGA604
 #socket_mPGA604_533Mhz
 #socket_mPGA604_800Mhz

src/cpu/intel/bga956/Kconfig

@@ -0,0 +1,4 @@
+config CPU_INTEL_SOCKET_BGA956
+	bool
+	default n
+	select CPU_INTEL_CORE2

src/cpu/intel/bga956/Makefile.inc

@@ -0,0 +1,13 @@
+obj-y += bga956.o
+subdirs-y += ../model_1067x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/sse
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+

src/cpu/intel/ep80579/Kconfig

@@ -0,0 +1,3 @@
+config CPU_INTEL_EP80579
+	bool
+	default false

src/cpu/intel/ep80579/Makefile.inc

@@ -0,0 +1,12 @@
+obj-y += ep80579.o
+driver-y += ep80579_init.o
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/sse
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+

src/cpu/intel/model_1067x/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_CORE2
+	bool
+	default y
+	select SMP
+	select HAVE_MOVNTI

src/cpu/intel/model_1067x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_1067x_init.o

src/cpu/intel/model_69x/Kconfig

@@ -0,0 +1,4 @@
+config CPU_INTEL_MODEL_69X
+	bool
+	default n
+	select SMP

src/cpu/intel/model_6dx/Kconfig

@@ -0,0 +1,4 @@
+config CPU_INTEL_MODEL_6DX
+	bool
+	default n
+	select SMP

src/cpu/intel/model_6xx/Kconfig

@@ -0,0 +1,4 @@
+config CPU_INTEL_MODEL_6XX
+	bool
+	default n
+	select SMP

src/cpu/intel/model_6xx/Makefile.inc

@@ -1,22 +1 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ron Minnich <rminnich@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
 driver-y += model_6xx_init.o
-

src/cpu/intel/model_f0x/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_MODEL_F0X
+	bool
+	default n
+	select SMP
+	select HAVE_MOVNTI

src/cpu/intel/model_f0x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_f0x_init.o

src/cpu/intel/model_f1x/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_MODEL_F1X
+	bool
+	default n
+	select SMP
+	select HAVE_MOVNTI

src/cpu/intel/model_f1x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_f1x_init.o

src/cpu/intel/model_f2x/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_MODEL_F2X
+	bool
+	default n
+	select SMP
+	select HAVE_MOVNTI

src/cpu/intel/model_f2x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_f2x_init.o

src/cpu/intel/model_f3x/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_MODEL_F3X
+	bool
+	default n
+	select SMP
+	select HAVE_MOVNTI

src/cpu/intel/model_f3x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_f3x_init.o

src/cpu/intel/model_f4x/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_MODEL_F4X
+	bool
+	default n
+	select SMP
+	select HAVE_MOVNTI

src/cpu/intel/model_f4x/Makefile.inc

@@ -0,0 +1 @@
+driver-y += model_f4x_init.o

src/cpu/intel/socket_mPGA478/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_SOCKET_MPGA478
+	bool
+	default false
+	select CPU_INTEL_MODEL_69X
+	select CPU_INTEL_MODEL_6DX

src/cpu/intel/socket_mPGA478/Makefile.inc

@@ -0,0 +1,14 @@
+obj-y += socket_mPGA478.o
+subdirs-y += ../model_69x
+subdirs-y += ../model_6dx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/sse
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+

src/cpu/intel/socket_mPGA479M/Kconfig

@@ -0,0 +1,5 @@
+config CPU_INTEL_SOCKET_MPGA479M
+	bool
+	default false
+	select CPU_INTEL_MODEL_69X
+	select CPU_INTEL_MODEL_6DX

src/cpu/intel/socket_mPGA479M/Makefile.inc

@@ -0,0 +1,14 @@
+obj-y += socket_mPGA479M.o
+subdirs-y += ../model_69x
+subdirs-y += ../model_6dx
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/sse
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+

src/cpu/intel/socket_mPGA603/Kconfig

@@ -0,0 +1,6 @@
+config CPU_INTEL_SOCKET_MPGA603
+	bool
+	default false
+	select CPU_INTEL_MODEL_F0X
+	select CPU_INTEL_MODEL_F1X
+	select CPU_INTEL_MODEL_F2X

src/cpu/intel/socket_mPGA603/Makefile.inc

@@ -0,0 +1,15 @@
+obj-y += socket_mPGA603_400Mhz.o
+subdirs-y += ../model_f0x
+subdirs-y += ../model_f1x
+subdirs-y += ../model_f2x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/sse
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+

src/cpu/intel/socket_mPGA604/Kconfig

@@ -0,0 +1,6 @@
+config CPU_INTEL_SOCKET_MPGA604
+	bool
+	default false
+	select CPU_INTEL_MODEL_F2X
+	select CPU_INTEL_MODEL_F3X
+	select CPU_INTEL_MODEL_F4X

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -0,0 +1,15 @@
+obj-y += socket_mPGA604.o
+subdirs-y += ../model_f2x
+subdirs-y += ../model_f3x
+subdirs-y += ../model_f4x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/fpu
+subdirs-y += ../../x86/mmx
+subdirs-y += ../../x86/sse
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+

src/cpu/x86/Kconfig

@@ -2,6 +2,10 @@ config SERIAL_CPU_INIT
 	bool
 	default y
 
+config WAIT_BEFORE_CPUS_INIT
+	bool
+	default n
+
 config UDELAY_TSC
 	bool
 	default n

src/mainboard/Kconfig

@@ -441,5 +441,14 @@ config COREBOOT_ROMSIZE_KB
 	help
 	  Map the config names to an integer.
 
+config ROM_SIZE
+	hex
+	default 0x20000 if COREBOOT_ROMSIZE_KB_128
+	default 0x40000 if COREBOOT_ROMSIZE_KB_256
+	default 0x80000 if COREBOOT_ROMSIZE_KB_512
+	default 0x100000 if COREBOOT_ROMSIZE_KB_1024
+	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
+	default 0x400000 if COREBOOT_ROMSIZE_KB_4096
+
 endmenu
 

src/mainboard/Makefile.romccboard.inc

@@ -44,15 +44,17 @@ obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
 
 ifdef POST_EVALUATION
 
+ROMCCFLAGS ?= -mcpu=p2
+
 $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
-	$(obj)/romcc -mcpu=p2 -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
+	$(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
 
 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
 $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
-	$(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	$(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
 else
 $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c
-	$(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	$(obj)/romcc -mcpu=$(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
 endif
 
 endif

src/mainboard/intel/Kconfig

@@ -1 +1,12 @@
-#
+choice
+        prompt "Mainboard model"
+        depends on VENDOR_INTEL
+
+source "src/mainboard/intel/eagleheights/Kconfig"
+source "src/mainboard/intel/jarrell/Kconfig"
+source "src/mainboard/intel/mtarvon/Kconfig"
+source "src/mainboard/intel/truxton/Kconfig"
+source "src/mainboard/intel/xe7501devkit/Kconfig"
+
+endchoice
+

src/mainboard/intel/eagleheights/Kconfig

@@ -0,0 +1,48 @@
+config BOARD_INTEL_EAGLEHEIGHTS
+	bool "EagleHeights"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_BGA956
+	select NORTHBRIDGE_INTEL_I3100
+	select SOUTHBRIDGE_INTEL_I3100
+	select SUPERIO_INTEL_I3100
+	select SUPERIO_SMSC_SMSCSUPERIO
+	select HAVE_PIRQ_TABLE
+	select HAVE_HIGH_TABLES
+	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+	select AP_IN_SIPI_WAIT
+	help
+          Intel EagleHeights mainboard.
+
+config MAINBOARD_DIR
+	string
+	default intel/eagleheights
+	depends on BOARD_INTEL_EAGLEHEIGHTS
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+	depends on BOARD_INTEL_EAGLEHEIGHTS
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_INTEL_EAGLEHEIGHTS
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_INTEL_EAGLEHEIGHTS
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_INTEL_EAGLEHEIGHTS
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EagleHeights"
+	depends on BOARD_INTEL_EAGLEHEIGHTS
+

src/mainboard/intel/eagleheights/Makefile.inc

@@ -0,0 +1,38 @@
+driver-y += mainboard.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-y += reset.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_MMCONF_SUPPORT=1 \
+	-DCONFIG_MMCONF_BASE_ADDRESS=0xe0000000
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/intel/eagleheights/devicetree.cb

@@ -0,0 +1,73 @@
+chip northbridge/intel/i3100
+        device pci_domain 0 on
+                device pci 00.0 on end # IMCH
+                device pci 00.1 on end # IMCH error status
+                device pci 01.0 on end # IMCH EDMA engine
+                device pci 02.0 on end # PCIe port A/A0
+                device pci 03.0 on end # PCIe port A1
+                chip southbridge/intel/i3100
+                        # PIRQ line -> legacy IRQ mappings
+			register "pirq_a_d" = "0x8b808a8a"
+                        register "pirq_e_h" = "0x85808080"
+
+                        device pci 1c.0 on end # PCIe port B0
+                        device pci 1c.1 off end # PCIe port B1
+                        device pci 1c.2 off end # PCIe port B2
+                        device pci 1c.3 off end # PCIe port B3
+                        device pci 1d.0 on end # USB (UHCI) 1
+                        device pci 1d.1 on end # USB (UHCI) 2
+                        device pci 1d.7 on end # USB (EHCI)
+                        device pci 1e.0 on end # PCI bridge
+                        device pci 1f.0 on     # LPC bridge
+                                chip superio/intel/i3100
+                                        device pnp 4e.4 on # Com1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 4e.5 on # Com2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                end
+				chip superio/smsc/smscsuperio
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.2 off	# Serial Port 4
+						io 0x60 = 0x2e8
+						irq 0x70 = 3
+					end
+					device pnp 2e.3 on	# Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 2
+					end
+					device pnp 2e.4 off	# Serial Port 3
+						io 0x60 = 0x3e8
+						irq 0x70 = 4
+					end
+					device pnp 2e.7 on	# PS/2 Keyboard / Mouse
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1    # PS/2 keyboard interrupt
+						irq 0x72 = 12   # PS/2 mouse interrupt
+					end
+					device pnp 2e.a off     # Runtime registers
+					       io 0x60 = 0x600
+					end
+				end
+                        end
+                        device pci 1f.2 on end # SATA
+                        device pci 1f.3 on end # SMBus
+			device pci 1f.4 on end # Performance counters
+                end
+        end
+        device apic_cluster 0 on
+                chip cpu/intel/bga956
+                        device apic 0 on end
+                end
+        end
+end
+

src/mainboard/intel/jarrell/Kconfig

@@ -0,0 +1,33 @@
+config BOARD_INTEL_JARRELL
+	bool "Jarrell"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_MPGA604
+	select NORTHBRIDGE_INTEL_E7520
+	select SOUTHBRIDGE_INTEL_PXHD
+	select SOUTHBRIDGE_INTEL_I82801ER
+	select SUPERIO_NSC_PC87427
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	help
+          Intel Jarrell mainboard.
+
+config MAINBOARD_DIR
+	string
+	default intel/jarrell
+	depends on BOARD_INTEL_JARRELL
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_INTEL_JARRELL
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_INTEL_JARRELL
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Jarrell"
+	depends on BOARD_INTEL_JARRELL
+

src/mainboard/intel/jarrell/Makefile.inc

@@ -0,0 +1,4 @@
+obj-y += reset.o
+ROMCCFLAGS := -mcpu=p4
+include $(src)/mainboard/Makefile.romccboard.inc
+

src/mainboard/intel/mtarvon/Kconfig

@@ -0,0 +1,41 @@
+config BOARD_INTEL_MTARVON
+	bool "Mt. Arvon"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_MPGA479M
+	select NORTHBRIDGE_INTEL_I3100
+	select SOUTHBRIDGE_INTEL_I3100
+	select SUPERIO_INTEL_I3100
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	help
+          Intel Mt. Arvon mainboard.
+
+config MAINBOARD_DIR
+	string
+	default intel/mtarvon
+	depends on BOARD_INTEL_MTARVON
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_INTEL_MTARVON
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_INTEL_MTARVON
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Mt. Arvon"
+	depends on BOARD_INTEL_MTARVON
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_INTEL_MTARVON
+
+config IRQ_SLOT_COUNT
+	int
+	default 1
+	depends on BOARD_INTEL_MTARVON

src/mainboard/intel/mtarvon/Makefile.inc

@@ -0,0 +1,3 @@
+ROMCCFLAGS := -mcpu=p4
+include $(src)/mainboard/Makefile.romccboard.inc
+

src/mainboard/intel/truxton/Kconfig

@@ -0,0 +1,43 @@
+config BOARD_INTEL_TRUXTON
+	bool "Truxton"
+	select ARCH_X86
+	select CPU_INTEL_EP80579
+	select NORTHBRIDGE_INTEL_I3100
+	select SOUTHBRIDGE_INTEL_I3100
+	select SUPERIO_INTEL_I3100
+	select SUPERIO_SMSC_SMSCSUPERIO
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	help
+          Intel Truxton mainboard.
+
+config MAINBOARD_DIR
+	string
+	default intel/truxton
+	depends on BOARD_INTEL_TRUXTON
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_INTEL_TRUXTON
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_INTEL_TRUXTON
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Truxton"
+	depends on BOARD_INTEL_TRUXTON
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_INTEL_TRUXTON
+
+config IRQ_SLOT_COUNT
+	int
+	default 1
+	depends on BOARD_INTEL_TRUXTON
+

src/mainboard/intel/truxton/Makefile.inc

@@ -0,0 +1,3 @@
+ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi
+include $(src)/mainboard/Makefile.romccboard.inc
+

src/mainboard/intel/xe7501devkit/Kconfig

@@ -0,0 +1,47 @@
+config BOARD_INTEL_XE7501DEVKIT
+	bool "xe7501 DevKit"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_MPGA604
+	select NORTHBRIDGE_INTEL_E7501
+	select SOUTHBRIDGE_INTEL_I82870
+	select SOUTHBRIDGE_INTEL_I82801CA
+	select SUPERIO_SMSC_LPC47B272
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	help
+          Intel xe7501 devkit mainboard.
+
+config MAINBOARD_DIR
+	string
+	default intel/xe7501devkit
+	depends on BOARD_INTEL_XE7501DEVKIT
+
+config LB_CKS_RANGE_START
+	int
+	default 128
+	depends on BOARD_INTEL_XE7501DEVKIT
+
+config LB_CKS_RANGE_END
+	int
+	default 130
+	depends on BOARD_INTEL_XE7501DEVKIT
+
+config LB_CKS_LOC
+	int
+	default 131
+	depends on BOARD_INTEL_XE7501DEVKIT
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EIDXE7501DEVKIT"
+	depends on BOARD_INTEL_XE7501DEVKIT
+
+config HAVE_OPTION_TABLE
+	bool
+	default y
+	depends on BOARD_INTEL_XE7501DEVKIT
+
+config IRQ_SLOT_COUNT
+	int
+	default 12
+	depends on BOARD_INTEL_XE7501DEVKIT

src/mainboard/intel/xe7501devkit/Makefile.inc

@@ -0,0 +1,13 @@
+ROMCCFLAGS := -mcpu=p4
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+ifeq ($(CONFIG_PCI_ROM_RUN),y)
+	ifeq ($(CONFIG_PCI_ROM_RUN),y)
+		obj-y += vgarom.o
+	else
+		obj-y += no_vgarom.o
+	endif
+else
+	obj-y += no_vgarom.o
+endif
+include $(src)/mainboard/Makefile.romccboard.inc
+

src/mainboard/sunw/Kconfig

@@ -1 +1,8 @@
-#
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_SUNW
+	
+source "src/mainboard/sunw/ultra40/Kconfig"
+
+endchoice
+

src/mainboard/sunw/ultra40/Kconfig

@@ -0,0 +1,130 @@
+config BOARD_SUNW_ULTRA40
+	bool "Ultra40"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_940
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_CK804
+	select SUPERIO_SMSC_LPC47M10X
+	select HAVE_PIRQ_TABLE
+	select USE_PRINTK_IN_CAR
+	select USE_DCACHE_RAM
+	help
+	 Sun Ultra40.
+
+config MAINBOARD_DIR
+	string
+	default sunw/ultra40
+	depends on BOARD_SUNW_ULTRA40
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xcf000
+	depends on BOARD_SUNW_ULTRA40
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x01000
+	depends on BOARD_SUNW_ULTRA40
+
+config APIC_ID_OFFSET
+	hex
+	default 0x10
+	depends on BOARD_SUNW_ULTRA40
+
+config HAVE_HARD_RESET
+	bool
+	default y
+	depends on BOARD_SUNW_ULTRA40
+
+config IOAPIC
+	bool
+	default y
+	depends on BOARD_SUNW_ULTRA40
+
+config K8_REV_F_SUPPORT
+	bool
+	default n
+	depends on BOARD_SUNW_ULTRA40
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_SUNW_ULTRA40
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on BOARD_SUNW_ULTRA40
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_SUNW_ULTRA40
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_SUNW_ULTRA40
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ultra40"
+	depends on BOARD_SUNW_ULTRA40
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_SUNW_ULTRA40
+
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+	depends on BOARD_SUNW_ULTRA40
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_SUNW_ULTRA40
+
+config MAX_CPUS
+	int
+	default 4
+	depends on BOARD_SUNW_ULTRA40
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_SUNW_ULTRA40
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_SUNW_ULTRA40
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_SUNW_ULTRA40
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_SUNW_ULTRA40
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_SUNW_ULTRA40
+
+config CONSOLE_VGA
+	bool
+	default y
+	depends on BOARD_SUNW_ULTRA40
+
+config PCI_ROM_RUN
+	bool
+	default y
+	depends on BOARD_SUNW_ULTRA40
+

src/mainboard/sunw/ultra40/Makefile.inc

@@ -0,0 +1,81 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=0 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/supermicro/Kconfig

@@ -1 +1,14 @@
-#
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_SUPERMICRO
+	
+source "src/mainboard/supermicro/h8dme/Kconfig"
+#source "src/mainboard/supermicro/h8dmr/Kconfig"
+#source "src/mainboard/supermicro/x6dai_g/Kconfig"
+#source "src/mainboard/supermicro/x6dhe_g/Kconfig"
+#source "src/mainboard/supermicro/x6dhe_g2/Kconfig"
+#source "src/mainboard/supermicro/x6dhr_ig/Kconfig"
+#source "src/mainboard/supermicro/x6dhr_ig2/Kconfig"
+
+endchoice
+

src/mainboard/supermicro/h8dme/Kconfig

@@ -0,0 +1,130 @@
+config BOARD_SUPERMICRO_H8DME
+	bool "h8dme"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_F
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SUPERIO_WINBOND_W83627HF
+	select HAVE_PIRQ_TABLE
+	select USE_PRINTK_IN_CAR
+	select USE_DCACHE_RAM
+	help
+	 h8dme
+
+config MAINBOARD_DIR
+	string
+	default supermicro/h8dme
+	depends on BOARD_SUPERMICRO_H8DME
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_SUPERMICRO_H8DME
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+	depends on BOARD_SUPERMICRO_H8DME
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x01000
+	depends on BOARD_SUPERMICRO_H8DME
+
+config APIC_ID_OFFSET
+	hex
+	default 0x10
+	depends on BOARD_SUPERMICRO_H8DME
+
+config HAVE_HARD_RESET
+	bool
+	default y
+	depends on BOARD_SUPERMICRO_H8DME
+
+config IOAPIC
+	bool
+	default y
+	depends on BOARD_SUPERMICRO_H8DME
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_SUPERMICRO_H8DME
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on BOARD_SUPERMICRO_H8DME
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_SUPERMICRO_H8DME
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_SUPERMICRO_H8DME
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ultra40"
+	depends on BOARD_SUPERMICRO_H8DME
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_SUPERMICRO_H8DME
+
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+	depends on BOARD_SUPERMICRO_H8DME
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_SUPERMICRO_H8DME
+
+config MAX_CPUS
+	int
+	default 4
+	depends on BOARD_SUPERMICRO_H8DME
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_SUPERMICRO_H8DME
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_SUPERMICRO_H8DME
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+	depends on BOARD_SUPERMICRO_H8DME
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_SUPERMICRO_H8DME
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 2
+	depends on BOARD_SUPERMICRO_H8DME
+
+config CONSOLE_VGA
+	bool
+	default y
+	depends on BOARD_SUPERMICRO_H8DME
+
+config PCI_ROM_RUN
+	bool
+	default y
+	depends on BOARD_SUPERMICRO_H8DME
+

src/mainboard/supermicro/h8dme/Makefile.inc

@@ -0,0 +1,82 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+driver-y += mainboard.o
+driver-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o
+
+# Needed by irq_tables and mptable and acpi_tables.
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=0 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/tyan/s2850/Kconfig

@@ -0,0 +1,65 @@
+config BOARD_TYAN_S2850
+	bool "Tyan S2850"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_940
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_AMD_AMD8111
+	select SUPERIO_WINBOND_W83627HF
+	select PIRQ_TABLE
+
+config MAINBOARD_DIR
+	string
+	default tyan/s2850
+	depends on BOARD_TYAN_S2850
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_TYAN_S2850
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_TYAN_S2850
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "s2850"
+	depends on BOARD_TYAN_S2850
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x2850
+	depends on BOARD_TYAN_S2850
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_TYAN_S2850
+
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+	depends on BOARD_TYAN_S2850
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_TYAN_S2850
+
+config MAX_CPUS
+	int
+	default 2
+	depends on BOARD_TYAN_S2850
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 1
+	depends on BOARD_TYAN_S2850
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_TYAN_S2850

src/mainboard/tyan/s2850/Makefile.inc

@@ -0,0 +1 @@
+include $(src)/mainboard/tyan/Makefile.s289x.inc

src/mainboard/tyan/s2875/Kconfig

@@ -0,0 +1,71 @@
+config BOARD_TYAN_S2875
+	bool "Tyan S2875"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_940
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_AMD_AMD8151
+	select SOUTHBRIDGE_AMD_AMD8111
+	select SUPERIO_WINBOND_W83627HF
+	select PIRQ_TABLE
+
+config MAINBOARD_DIR
+	string
+	default tyan/s2875
+	depends on BOARD_TYAN_S2875
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_TYAN_S2875
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_TYAN_S2875
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "s2875"
+	depends on BOARD_TYAN_S2875
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x2875
+	depends on BOARD_TYAN_S2875
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_TYAN_S2875
+
+config HAVE_FAILOVER_BOOT
+	bool
+	default n
+	depends on BOARD_TYAN_S2875
+
+config USE_FAILOVER_IMAGE
+	bool
+	default n
+	depends on BOARD_TYAN_S2875
+
+config MAX_CPUS
+	int
+	default 4
+	depends on BOARD_TYAN_S2875
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_TYAN_S2875
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+	depends on BOARD_TYAN_S2875
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_TYAN_S2875

src/mainboard/tyan/s2875/Makefile.inc

@@ -0,0 +1 @@
+include $(src)/mainboard/tyan/Makefile.s289x.inc

src/mainboard/via/Kconfig

@@ -2,8 +2,13 @@ choice
 	prompt "Mainboard model"
 	depends on VENDOR_VIA
 
-source "src/mainboard/via/vt8454c/Kconfig"
+source "src/mainboard/via/epia/Kconfig"
+source "src/mainboard/via/epia-cn/Kconfig"
+source "src/mainboard/via/epia-m/Kconfig"
+source "src/mainboard/via/epia-m700/Kconfig"
 source "src/mainboard/via/epia-n/Kconfig"
+source "src/mainboard/via/pc2500e/Kconfig"
+source "src/mainboard/via/vt8454c/Kconfig"
 
 endchoice
 

src/mainboard/via/epia-cn/Kconfig

@@ -0,0 +1,45 @@
+config BOARD_VIA_EPIA_CN
+	bool "EPIA-CN"
+	select ARCH_X86
+	select CPU_VIA_C7
+	select NORTHBRIDGE_VIA_CN700
+	select SOUTHBRIDGE_VIA_VT8237R
+	select SUPERIO_VIA_VT1211
+	select HAVE_PIRQ_TABLE
+	help
+	  VIA EPIA-CN mainboard.
+
+config MAINBOARD_DIR
+	string
+	default via/epia-cn
+	depends on BOARD_VIA_EPIA_CN
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffef0000
+#	depends on BOARD_VIA_EPIA_CN
+#
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_VIA_EPIA_CN
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EPIA_CN"
+	depends on BOARD_VIA_EPIA_CN
+
+config VIDEO_MB
+	int
+	default 32
+	depends on BOARD_VIA_EPIA_CN
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_VIA_EPIA_CN
+
+config IRQ_SLOT_COUNT
+	int
+	default 9
+	depends on BOARD_VIA_EPIA_CN

src/mainboard/via/epia-cn/Makefile.inc

@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+initobj-y += crt0.o
+obj-y += mainboard.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/via/epia-m/Kconfig

@@ -0,0 +1,41 @@
+config BOARD_VIA_EPIA_M
+	bool "EPIA-M"
+	select ARCH_X86
+	select CPU_VIA_C3
+	select NORTHBRIDGE_VIA_VT8623
+	select SOUTHBRIDGE_VIA_VT8235
+	select SOUTHBRIDGE_RICOH_RL5C476
+	select SUPERIO_VIA_VT1211
+	select HAVE_PIRQ_TABLE
+	help
+	  VIA EPIA-M mainboard.
+
+config MAINBOARD_DIR
+	string
+	default via/epia-m
+	depends on BOARD_VIA_EPIA_M
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffef0000
+#	depends on BOARD_VIA_EPIA_M
+
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_VIA_EPIA_M
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EPIA_M"
+	depends on BOARD_VIA_EPIA_M
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_VIA_EPIA_M
+
+config IRQ_SLOT_COUNT
+	int
+	default 5
+	depends on BOARD_VIA_EPIA_M

src/mainboard/via/epia-m/Makefile.inc

@@ -0,0 +1,65 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+initobj-y += crt0.o
+obj-y += mainboard.o
+obj-y += vgabios.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/northbridge/via/vx800/romstrap.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/northbridge/via/vx800/romstrap.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/via/epia-m/auto.c

@@ -20,7 +20,7 @@
 
 /*
  */
-void udelay(int usecs) 
+void udelay(unsigned usecs) 
 {
 	int i;
 	for(i = 0; i < usecs; i++)

src/mainboard/via/epia-m700/Kconfig

@@ -0,0 +1,44 @@
+config BOARD_VIA_EPIA_M700
+	bool "EPIA-M700"
+	select ARCH_X86
+	select CPU_VIA_C7
+	select NORTHBRIDGE_VIA_VX800
+	select SUPERIO_WINBOND_W83697HF
+	select HAVE_PIRQ_TABLE
+	help
+	  VIA EPIA-M700 mainboard.
+
+config MAINBOARD_DIR
+	string
+	default via/epia-m700
+	depends on BOARD_VIA_EPIA_M700
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffef0000
+	depends on BOARD_VIA_EPIA_M700
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_VIA_EPIA_M700
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EPIA_M700"
+	depends on BOARD_VIA_EPIA_M700
+
+config VIDEO_MB
+	int
+	default 64
+	depends on BOARD_VIA_EPIA_M700
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_VIA_EPIA_M700
+
+config IRQ_SLOT_COUNT
+	int
+	default 13
+	depends on BOARD_VIA_EPIA_M700

src/mainboard/via/epia-m700/Makefile.inc

@@ -0,0 +1,64 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+initobj-y += crt0.o
+obj-y += mainboard.o
+obj-y += wakeup.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/northbridge/via/vx800/romstrap.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/northbridge/via/vx800/romstrap.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/via/car/cache_as_ram.inc
+crt0-y += cache_as_ram_auto.inc
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/via/epia-n/Kconfig

@@ -6,7 +6,6 @@ config BOARD_VIA_EPIA_N
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SUPERIO_WINBOND_W83697HF
 	select HAVE_PIRQ_TABLE
-	select USE_PRINTK_IN_CAR
 	help
 	  VIA EPIA-N mainboard.
 

src/mainboard/via/epia-n/Makefile.inc

@@ -44,9 +44,7 @@ crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
 
 ifdef POST_EVALUATION
 
-MAINBOARD_OPTIONS=\
+MAINBOARD_OPTIONS=
-	-DCONFIG_USE_PRINTK_IN_CAR=1 \
-	-DCONFIG_HAVE_HIGH_TABLES=1
 
 $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
 	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@

src/mainboard/via/epia/Kconfig

@@ -0,0 +1,35 @@
+config BOARD_VIA_EPIA
+	bool "EPIA"
+	select ARCH_X86
+	select CPU_VIA_C3
+	select NORTHBRIDGE_VIA_VT8601
+	select SOUTHBRIDGE_VIA_VT8231
+	select SUPERIO_WINBOND_W83627HF
+	select HAVE_PIRQ_TABLE
+	help
+	  VIA EPIA mainboard.
+
+config MAINBOARD_DIR
+	string
+	default via/epia
+	depends on BOARD_VIA_EPIA
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffef0000
+#	depends on BOARD_VIA_EPIA
+#
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_VIA_EPIA
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "EPIA"
+	depends on BOARD_VIA_EPIA
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_VIA_EPIA

src/mainboard/via/epia/Makefile.inc

@@ -0,0 +1,58 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+initobj-y += crt0.o
+obj-y += mainboard.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/mainboard/via/epia/auto.c

@@ -16,7 +16,7 @@
 
 /*
  */
-void udelay(int usecs) 
+void udelay(unsigned usecs) 
 {
 	int i;
 	for (i = 0; i < usecs; i++)

src/mainboard/via/pc2500e/Kconfig

@@ -0,0 +1,45 @@
+config BOARD_VIA_PC2500E
+	bool "PC2500E"
+	select ARCH_X86
+	select CPU_VIA_C7
+	select NORTHBRIDGE_VIA_CN700
+	select SOUTHBRIDGE_VIA_VT8237R
+	select SUPERIO_ITE_IT8716F
+	select HAVE_PIRQ_TABLE
+	help
+	  VIA PC2500E mainboard.
+
+config MAINBOARD_DIR
+	string
+	default via/pc2500e
+	depends on BOARD_VIA_PC2500E
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffef0000
+#	depends on BOARD_VIA_PC2500E
+#
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_VIA_PC2500E
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "PC2500E"
+	depends on BOARD_VIA_PC2500E
+
+config VIDEO_MB
+	int
+	default 32
+	depends on BOARD_VIA_PC2500E
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_VIA_PC2500E
+
+config IRQ_SLOT_COUNT
+	int
+	default 10
+	depends on BOARD_VIA_PC2500E

src/mainboard/via/pc2500e/Makefile.inc

@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+initobj-y += crt0.o
+obj-y += mainboard.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
+crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
+crt0-y += auto.inc
+crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

src/northbridge/amd/Kconfig

@@ -1,8 +1,5 @@
 source src/northbridge/amd/amdk8/Kconfig
 source src/northbridge/amd/gx2/Kconfig
-
+source src/northbridge/amd/amdfam10/Kconfig
-#source src/northbridge/amd/amdfam10/Kconfig
-#source src/northbridge/amd/amdht/Kconfig
-#source src/northbridge/amd/amdmct/Kconfig
 #source src/northbridge/amd/gx1/Kconfig
 #source src/northbridge/amd/lx/Kconfig

src/northbridge/amd/Makefile.inc

@@ -1,7 +1,5 @@
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) += amdfam10
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDHT) += amdht
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDMCT) += amdmct
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx

src/northbridge/amd/amdfam10/Kconfig

@@ -0,0 +1,34 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_AMDFAM10
+	bool
+	default n
+
+config AGP_APERTURE_SIZE
+	hex
+	default 0x4000000
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
+source src/northbridge/amd/amdfam10/root_complex/Kconfig

src/northbridge/amd/amdfam10/Makefile.inc

@@ -0,0 +1,12 @@
+driver-y += northbridge.o
+driver-y += misc_control.o
+
+obj-$(CONFIG_HAVE_ACPI_TABLES) += amdfam10_acpi.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr1.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr2.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr4.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += sspr5.o
+
+obj-y += get_pci1234.o

src/northbridge/amd/amdfam10/root_complex/Kconfig

@@ -0,0 +1,4 @@
+config NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
+	bool
+	default n
+

src/northbridge/amd/amdk8/Kconfig

@@ -24,10 +24,12 @@ config NORTHBRIDGE_AMD_AMDK8
 config AGP_APERTURE_SIZE
 	hex
 	default 0x4000000
+	depends on NORTHBRIDGE_AMD_AMDK8
 
 config HAVE_HIGH_TABLES
 	bool
 	default y
+	depends on NORTHBRIDGE_AMD_AMDK8
 
 config HYPERTRANSPORT_PLUGIN_SUPPORT
 	bool

src/northbridge/intel/Kconfig

@@ -1,10 +1,10 @@
-#source src/northbridge/intel/e7501/Kconfig
+source src/northbridge/intel/e7501/Kconfig
-#source src/northbridge/intel/e7520/Kconfig
+source src/northbridge/intel/e7520/Kconfig
-#source src/northbridge/intel/e7525/Kconfig
+source src/northbridge/intel/e7525/Kconfig
-#source src/northbridge/intel/i3100/Kconfig
+source src/northbridge/intel/i3100/Kconfig
 source src/northbridge/intel/i440bx/Kconfig
 source src/northbridge/intel/i82810/Kconfig
-#source src/northbridge/intel/i82830/Kconfig
+source src/northbridge/intel/i82830/Kconfig
-#source src/northbridge/intel/i855gme/Kconfig
+source src/northbridge/intel/i855gme/Kconfig
-#source src/northbridge/intel/i855pm/Kconfig
+source src/northbridge/intel/i855pm/Kconfig
 source src/northbridge/intel/i945/Kconfig

src/northbridge/intel/Makefile.inc

@@ -1,10 +1,10 @@
-#subdirs-y += e7501
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501
-#subdirs-y += e7520
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520
-#subdirs-y += e7525
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525
-#subdirs-y += i3100
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100
-subdirs-y += i440bx
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx
-subdirs-y += i82810
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
-#subdirs-y += i82830
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
-#subdirs-y += i855gme
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855GME) += i855gme
-#subdirs-y += i855pm
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855PM) += i855pm
-subdirs-y += i945
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945

src/northbridge/intel/e7501/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_E7501
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_E7501

src/northbridge/intel/e7501/Makefile.inc

@@ -0,0 +1 @@
+obj-y += northbridge.o

src/northbridge/intel/e7520/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_E7520
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_E7520

src/northbridge/intel/e7520/Makefile.inc

@@ -0,0 +1,5 @@
+driver-y += northbridge.o
+driver-y += pciexp_porta.o
+driver-y += pciexp_porta1.o
+driver-y += pciexp_portb.o
+driver-y += pciexp_portc.o

src/northbridge/intel/e7525/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_E7525
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_E7525

src/northbridge/intel/e7525/Makefile.inc

@@ -0,0 +1,5 @@
+driver-y += northbridge.o
+driver-y += pciexp_porta.o
+driver-y += pciexp_porta1.o
+driver-y += pciexp_portb.o
+driver-y += pciexp_portc.o

src/northbridge/intel/i3100/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_I3100
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_I3100

src/northbridge/intel/i3100/Makefile.inc

@@ -0,0 +1,3 @@
+driver-y += northbridge.o
+driver-y += pciexp_porta.o
+driver-y += pciexp_porta_ep80579.o

src/northbridge/intel/i440bx/Kconfig

@@ -22,3 +22,7 @@ config NORTHBRIDGE_INTEL_I440BX
 	bool
 	default n
 
+config HAVE_HIGH_TABLES
+	bool
+	default y
+

src/northbridge/intel/i440bx/Makefile.inc

@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-driver-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += northbridge.o
+driver-y += northbridge.o
 

src/northbridge/intel/i82810/Kconfig

@@ -21,3 +21,9 @@
 config NORTHBRIDGE_INTEL_I82810
 	bool
 	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_I82810
+

src/northbridge/intel/i82810/Makefile.inc

@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-driver-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += northbridge.o
+driver-y += northbridge.o
 

src/northbridge/intel/i82830/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_I82830
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_I82830

src/northbridge/intel/i82830/Makefile.inc

@@ -0,0 +1,2 @@
+driver-y += northbridge.o
+driver-y += vga.o

src/northbridge/intel/i855gme/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_I855GME
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_I855GME

src/northbridge/intel/i855gme/Makefile.inc

@@ -0,0 +1 @@
+obj-y += northbridge.o

src/northbridge/intel/i855pm/Kconfig

@@ -0,0 +1,8 @@
+config NORTHBRIDGE_INTEL_I855PM
+	bool
+	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_I855PM

src/northbridge/intel/i855pm/Makefile.inc

@@ -0,0 +1 @@
+obj-y += northbridge.o

src/northbridge/intel/i945/Kconfig

@@ -20,3 +20,9 @@
 config NORTHBRIDGE_INTEL_I945
 	bool
 	default n
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+	depends on NORTHBRIDGE_INTEL_I945
+

src/northbridge/intel/i945/Makefile.inc

@@ -17,8 +17,6 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += northbridge.o
+driver-y += northbridge.o
-driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += gma.o
+driver-y += gma.o
-ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o
-	obj-$(CONFIG_NORTHBRIDGE_INTEL_I945) += acpi.o
-endif