set up interrupt values for the southbridge, and add a function to

manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c 
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/devices/pci_device.c

@@ -1161,7 +1161,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
     Tell the EISA int controller this int must be level triggered
     THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
 */
-static void pci_level_irq(unsigned char intNum)
+void pci_level_irq(unsigned char intNum)
 {
 	unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
 

src/mainboard/olpc/rev_a/Config.lb

@@ -135,8 +135,13 @@ chip northbridge/amd/gx2
 		device pci 1.1 on end
       		chip southbridge/amd/cs5536
                         register "enable_gpio0_inta" = "1"
-		      register "enable_ide_nand_flash" = "1"
-		      register "enable_uarta" = "1"
+			register "enable_ide_nand_flash" = "1"
+			register "enable_uarta" = "1"
+			register "audio_irq" = "5"
+			register "usbf4_irq" = "10"
+			register "usbf5_irq" = "0"
+			register "usbf6_irq" = "0"
+			register "usbf7_irq" = "0"
         		device pci d.0 on end	# Realtek 8139 LAN
         		device pci f.0 on end	# ISA Bridge
         		device pci f.2 on end	# IDE Controller

src/mainboard/olpc/rev_a/mainboard.c

@@ -9,13 +9,16 @@
 
 
 static void init(struct device *dev) {
+/*
 	unsigned bus = 0;
 	unsigned devfn = PCI_DEVFN(0xf, 4);
 	device_t usb = NULL;
 	unsigned char usbirq = 0xa;
+*/
 
 	printk_debug("OLPC REVA ENTER %s\n", __FUNCTION__);
 
+#if 0
 	/* I can't think of any reason NOT to just set this. If it turns out we want this to be
 	  * conditional we can make it a config variable later.
 	  */
@@ -28,6 +31,7 @@ static void init(struct device *dev) {
 	} else {
 		pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
 	}
+#endif
 	printk_debug("OLPC REVA EXIT %s\n", __FUNCTION__);
 }
 

src/southbridge/amd/cs5536/chip.h

@@ -10,6 +10,14 @@ struct southbridge_amd_cs5536_config {
  	int enable_gpio0_inta; 	/* almost always will be true */
 	int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
 	int enable_uarta; 		/* internal uarta interrupt enable */
+	/* following are IRQ numbers for various southbridge resources. */
+	/* I have guessed at some things, as I still don't have an lspci from anyone */
+	int ide_irq;		/* f.2 */
+	int audio_irq; 		/* f.3 */
+	int usbf4_irq;		/* f.4 */
+	int usbf5_irq;		/* f.5 */
+	int usbf6_irq;		/* f.6 */
+	int usbf7_irq; 		/* f.7 */
 };
 
 #endif	/* _SOUTHBRIDGE_AMD_CS5536 */

src/southbridge/amd/cs5536/cs5536.c

@@ -63,6 +63,21 @@ enable_ide_nand_flash(){
 	printk_err("cs5536: EXIT %s\n", __FUNCTION__);
 }
 
+/* note: this is a candidate for inclusion in src/devices/pci_device.c */
+void
+setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned device, unsigned fn){
+	if (irq)  {
+		unsigned devfn = PCI_DEVFN(device,fn);
+		device_t dev  = dev_find_slot(bus, devfn);
+		if (dev) {
+			pci_write_config8(dev, PCI_INTERRUPT_LINE, irq);
+			if (level)
+				pci_level_irq(irq);
+		}
+		else
+			printk_err("%s: Can't find %s at 0x%x\n", __FUNCTION__, name, devfn);
+	}
+}
 
 static void southbridge_enable(struct device *dev)
 {
@@ -109,7 +124,14 @@ static void southbridge_enable(struct device *dev)
 	printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
 	if (sb->enable_ide_nand_flash) {
 		enable_ide_nand_flash();
-	}		
+	}
+
+	/* irq handling */
+	setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
+	setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
+	setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
+	setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
+	setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
 	
 }