soc/intel/jasperlake: Use boolean type where applicable
Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Michael Strosche
Felix Singer
parent
1855cb4644
commit
8900323c4f
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@ -19,6 +19,7 @@
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <stdint.h>
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#include <stdbool.h>
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#define MAX_HD_AUDIO_DMIC_LINKS 2
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#define MAX_HD_AUDIO_SNDW_LINKS 4
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@ -76,15 +77,15 @@ struct soc_intel_jasperlake_config {
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uint32_t gen4_dec;
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/* Enable S0iX support */
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int s0ix_enable;
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bool s0ix_enable;
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/* Enable DPTF support */
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int dptf_enable;
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bool dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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bool deep_s3_enable_ac;
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bool deep_s3_enable_dc;
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bool deep_s5_enable_ac;
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bool deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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@ -107,8 +108,12 @@ struct soc_intel_jasperlake_config {
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SaGv_Enabled,
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} SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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/* Rank Margin Tool
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*
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* true: Enable
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* false: Disable
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*/
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bool RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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@ -125,22 +130,22 @@ struct soc_intel_jasperlake_config {
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/* SATA related */
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uint8_t SataMode;
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uint8_t SataSalpSupport;
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uint8_t SataPortsEnable[8];
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uint8_t SataPortsDevSlp[8];
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bool SataSalpSupport;
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bool SataPortsEnable[8];
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bool SataPortsDevSlp[8];
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/* Audio related */
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uint8_t PchHdaDspEnable;
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uint8_t PchHdaAudioLinkHdaEnable;
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uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
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uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
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uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
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bool PchHdaDspEnable;
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bool PchHdaAudioLinkHdaEnable;
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bool PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
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bool PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
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bool PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
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uint8_t PchHdaIDispLinkTmode;
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uint8_t PchHdaIDispLinkFrequency;
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uint8_t PchHdaIDispCodecDisconnect;
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bool PchHdaIDispCodecDisconnect;
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/* PCIe Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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/* PCIe output clocks type to PCIe devices.
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* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
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* 0xFF: not used */
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@ -150,7 +155,7 @@ struct soc_intel_jasperlake_config {
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uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
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/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
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uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
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/* PCIe RP L1 substate */
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enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
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@ -159,26 +164,26 @@ struct soc_intel_jasperlake_config {
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struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS];
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/* SMBus */
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uint8_t SmbusEnable;
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bool SmbusEnable;
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/* eMMC and SD */
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uint8_t ScsEmmcHs400Enabled;
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bool ScsEmmcHs400Enabled;
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/* Enable if SD Card Power Enable Signal is Active High */
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uint8_t SdCardPowerEnableActiveHigh;
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bool SdCardPowerEnableActiveHigh;
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/* VR Config Settings for IA Core */
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uint16_t ImonSlope;
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uint16_t ImonOffset;
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/* Gfx related */
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uint8_t SkipExtGfxScan;
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bool SkipExtGfxScan;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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bool eist_enable;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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bool enable_c6dram;
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/*
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* SerialIO device mode selection:
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@ -223,21 +228,21 @@ struct soc_intel_jasperlake_config {
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unsigned int sdcard_cd_gpio;
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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bool pch_isclk;
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/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
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bool CnviBtAudioOffload;
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/* Tcss */
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uint8_t TcssXhciEn;
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uint8_t TcssXdciEn;
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bool TcssXhciEn;
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bool TcssXdciEn;
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/*
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* Override GPIO PM configuration:
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* 0: Use FSP default GPIO PM program,
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* 1: coreboot to override GPIO PM program
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* false: Use FSP default GPIO PM program,
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* true: coreboot to override GPIO PM program
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*/
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uint8_t gpio_override_pm;
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bool gpio_override_pm;
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/*
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* GPIO PM configuration: 0 to disable, 1 to enable power gating
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@ -259,28 +264,40 @@ struct soc_intel_jasperlake_config {
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uint8_t DdiPortAConfig;
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uint8_t DdiPortBConfig;
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/* Enable(1)/Disable(0) HPD */
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uint8_t DdiPortAHpd;
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uint8_t DdiPortBHpd;
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uint8_t DdiPortCHpd;
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uint8_t DdiPort1Hpd;
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uint8_t DdiPort2Hpd;
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uint8_t DdiPort3Hpd;
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uint8_t DdiPort4Hpd;
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/* HDP config
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*
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* true: Enable HDB
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* false: Disable HDP
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*/
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bool DdiPortAHpd;
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bool DdiPortBHpd;
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bool DdiPortCHpd;
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bool DdiPort1Hpd;
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bool DdiPort2Hpd;
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bool DdiPort3Hpd;
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bool DdiPort4Hpd;
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/* Enable(1)/Disable(0) DDC */
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uint8_t DdiPortADdc;
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uint8_t DdiPortBDdc;
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uint8_t DdiPortCDdc;
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uint8_t DdiPort1Ddc;
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uint8_t DdiPort2Ddc;
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uint8_t DdiPort3Ddc;
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uint8_t DdiPort4Ddc;
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/* DDC config
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*
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* true: Enable DDC
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* false: Disable DDC
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*/
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bool DdiPortADdc;
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bool DdiPortBDdc;
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bool DdiPortCDdc;
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bool DdiPort1Ddc;
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bool DdiPort2Ddc;
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bool DdiPort3Ddc;
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bool DdiPort4Ddc;
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/* Hybrid storage mode enable (1) / disable (0)
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/* Hybrid storage mode
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* This mode makes FSP detect Optane and NVME and set PCIe lane mode
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* accordingly */
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uint8_t HybridStorageMode;
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* accordingly
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*
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* true: Enable Hybrid storage mode
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* false Dsiable Hybrid storage mode
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*/
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bool HybridStorageMode;
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/*
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* Override CPU flex ratio value:
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@ -294,12 +311,14 @@ struct soc_intel_jasperlake_config {
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uint8_t cpu_ratio_override;
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/* Skip CPU replacement check
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* 0: disable
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* 1: enable
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*
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* Setting this option to skip CPU replacement check to avoid the forced MRC training
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* for the platforms with soldered down SOC.
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*
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* false: disable
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* true: enable
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*/
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uint8_t SkipCpuReplacementCheck;
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bool SkipCpuReplacementCheck;
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/*
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* SLP_S3 Minimum Assertion Width Policy
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@ -377,7 +396,7 @@ struct soc_intel_jasperlake_config {
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* Disable Fast Slew Rate for Deep Package C States based on
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* Acoustic Noise Mitigation feature enabled.
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*/
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uint8_t FastPkgCRampDisable;
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bool FastPkgCRampDisable;
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/*
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* Slew Rate configuration for Deep Package C States for VCCIN VR domain
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@ -393,9 +412,11 @@ struct soc_intel_jasperlake_config {
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/*
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* Enable or Disable Acoustic Noise Mitigation feature.
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* 0: Disabled ; 1: Enabled
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*
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* false: Disabled
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* true: Enabled
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*/
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uint8_t AcousticNoiseMitigation;
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bool AcousticNoiseMitigation;
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/*
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* Acoustic Noise Mitigation Range.Defines the maximum Pre-Wake
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