GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/google/zoombini/variants/meowth: Add rev 2 gpio changes 

Change GPIO settings for meowth rev 2 boards.

Changes include:
- GPP_B7 set to no-connect
- GPP_C1 set to no-connect
- GPP_D8 set to no-connect
- GPP_D9 (PP3300_WLAN_EN) set as output with initial value high
- GPP_E9 (DCI_CLK) set to no-connect
- GPP_E10 (DCI_DATA) set to no-connect

BUG=b:72202352
BRANCH=none
TEST=none

Change-Id: I2e6d049faaa0a70b40ceb47aaf81a81d820dd4c1
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2018-01-21 22:26:33 -08:00 committed by Martin Roth
parent af0e7d18a7
commit 896b6ab470
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/google/zoombini/variants/meowth/gpio.c
View File

@ -49,8 +49,7 @@ static const struct pad_config gpio_table[] = {
/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),
/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE),
/* SRCCLKREQ1# */ PAD_NC(GPP_B6, NONE),
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,
NF1), /* PCIE_8_WLAN_CLKREQ_ODL */
/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE),
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP,
NF1), /* PCIE_NVME_CLKREQ_ODL */
/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE),
@ -84,8 +83,7 @@ static const struct pad_config gpio_table[] = {
NF1), /* PCH_FPMCU_SPI_MOSI_R */
/* SML1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* GPP_B23_STRAP */
/* SMBCLK */ PAD_NC(GPP_C0, NONE),
/* SMBDATA */ PAD_CFG_GPI(GPP_C1, NONE,
DEEP), /* PCIE_8_WLAN_WAKE_ODL */
/* SMBDATA */ PAD_NC(GPP_C1, NONE),
/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP), /* GPP_C2_STRAP */
/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* PCH_SAR1_INT_L */
/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* PCH_SAR0_INT_L */
@ -125,8 +123,8 @@ static const struct pad_config gpio_table[] = {
/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
/* ISH_I2C1_SDA */ PAD_CFG_GPO(GPP_D7, 1, DEEP), /* FCAM_RST_L */
/* ISH_I2C1_SCL */ PAD_CFG_GPO(GPP_D8, 0, DEEP), /* DMIC_PWR_EN */
/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE),
/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
/* ISH_SPI_CS# */ PAD_CFG_GPO(GPP_D9, 1, DEEP), /* PP3300_WLAN_EN */
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* FCAM_PWR_EN */
/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE),
/* ISH_SPI_MOSI */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */
@ -152,8 +150,8 @@ static const struct pad_config gpio_table[] = {
/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),
/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),
/* SATALED# */ PAD_NC(GPP_E8, NONE),
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2), /* DCI_CLK */
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF2), /* DCI_DATA */
/* USB2_OCO# */ PAD_NC(GPP_E9, NONE),
/* USB2_OC1# */ PAD_NC(GPP_E10, NONE),
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,
NF1), /* USB_C0_OC_ODL */
/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,