soc/intel/cannonlake: Use common p2sb driver

Add common p2sb driver support.

TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.

Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-10-26 12:02:30 -07:00 committed by Aaron Durbin
parent a3cbbf7652
commit 899f5ffbdd
2 changed files with 4 additions and 0 deletions

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@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_LPC select SOC_INTEL_COMMON_BLOCK_LPC
select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_RTC

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@ -83,4 +83,7 @@
#define TCO_BASE_ADDRESS 0x400 #define TCO_BASE_ADDRESS 0x400
#define TCO_BASE_SIZE 0x20 #define TCO_BASE_SIZE 0x20
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#define P2SB_SIZE (16 * MiB)
#endif #endif