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nb/intel/sandybridge: Use cached CPUID 

Now that we have it, we might as well pass it around.

Tested on Asus P8Z77-V LX2, still boots fine.

Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-03-21 13:23:32 +01:00 committed by Patrick Georgi
parent a6a64183d6
commit 89ae6b8fc2
4 changed files with 6 additions and 9 deletions
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9
src/northbridge/intel/sandybridge/raminit_common.c
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@ -168,15 +168,14 @@ void dram_xover(ramctr_timing *ctrl)
static void dram_odt_stretch(ramctr_timing *ctrl, int channel) static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
{ {
u32 addr, cpu, stretch; u32 addr, stretch;
stretch = ctrl->ref_card_offset[channel]; stretch = ctrl->ref_card_offset[channel];
/* /*
* ODT stretch: * ODT stretch:
* Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel.
*/ */
cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) {
if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
if (stretch == 2) if (stretch == 2)
stretch = 3; stretch = 3;
@ -2992,10 +2991,8 @@ void set_scrambling_seed(ramctr_timing *ctrl)
} }
} }
void set_wmm_behavior(void) void set_wmm_behavior(const u32 cpu)
{ {
u32 cpu = cpu_get_cpuid();
if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
MCHBAR32(SC_WDBWM) = 0x141d1519; MCHBAR32(SC_WDBWM) = 0x141d1519;
} else { } else {

2
src/northbridge/intel/sandybridge/raminit_common.h
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@ -181,7 +181,7 @@ void normalize_training(ramctr_timing *ctrl);
void write_controller_mr(ramctr_timing *ctrl); void write_controller_mr(ramctr_timing *ctrl);
int channel_test(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl);
void set_scrambling_seed(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl);
void set_wmm_behavior(void); void set_wmm_behavior(const u32 cpu);
void prepare_training(ramctr_timing *ctrl); void prepare_training(ramctr_timing *ctrl);
void set_read_write_timings(ramctr_timing *ctrl); void set_read_write_timings(ramctr_timing *ctrl);
void set_normal_operation(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl);

2
src/northbridge/intel/sandybridge/raminit_ivy.c
View File

@ -609,7 +609,7 @@ int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in
MCHBAR32(SCHED_CBIT) = 0x10100005; MCHBAR32(SCHED_CBIT) = 0x10100005;
/* Set up watermarks and starvation counter */ /* Set up watermarks and starvation counter */
set_wmm_behavior(); set_wmm_behavior(ctrl->cpu);
/* Clear IO reset bit */ /* Clear IO reset bit */
MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);

2
src/northbridge/intel/sandybridge/raminit_sandy.c
View File

@ -433,7 +433,7 @@ int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in
MCHBAR32(SCHED_CBIT) = 0x10100005; MCHBAR32(SCHED_CBIT) = 0x10100005;
/* Set up watermarks and starvation counter */ /* Set up watermarks and starvation counter */
set_wmm_behavior(); set_wmm_behavior(ctrl->cpu);
/* Clear IO reset bit */ /* Clear IO reset bit */
MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);