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util/inteltool: Add support for Tiger Lake chips detection and GPIOs 

Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.

TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Michał Żygowski 2021-07-09 16:00:16 +02:00 committed by Michael Niewöhner
parent 0de0254a1f
commit 8ac40f3ea7
6 changed files with 1503 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
util/inteltool/gpio.c
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@ -1040,6 +1040,11 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C621:
case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C622:
case PCI_DEVICE_ID_INTEL_C624: case PCI_DEVICE_ID_INTEL_C624:
@ -1077,6 +1082,17 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246: case PCI_DEVICE_ID_INTEL_CM246:
case PCI_DEVICE_ID_INTEL_Q570:
case PCI_DEVICE_ID_INTEL_Z590:
case PCI_DEVICE_ID_INTEL_H570:
case PCI_DEVICE_ID_INTEL_B560:
case PCI_DEVICE_ID_INTEL_H510:
case PCI_DEVICE_ID_INTEL_WM590:
case PCI_DEVICE_ID_INTEL_QM580:
case PCI_DEVICE_ID_INTEL_HM570:
case PCI_DEVICE_ID_INTEL_C252:
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
print_gpio_groups(sb); print_gpio_groups(sb);
return 0; return 0;

23
util/inteltool/gpio_groups.c
View File

@ -17,6 +17,7 @@
#include "gpio_names/icelake.h" #include "gpio_names/icelake.h"
#include "gpio_names/lewisburg.h" #include "gpio_names/lewisburg.h"
#include "gpio_names/sunrise.h" #include "gpio_names/sunrise.h"
#include "gpio_names/tigerlake.h"
#define SBBAR_SIZE (16 * MiB) #define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB) #define PCR_PORT_SIZE (64 * KiB)
@ -174,6 +175,28 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
*community_count = ARRAY_SIZE(icelake_pch_h_communities); *community_count = ARRAY_SIZE(icelake_pch_h_communities);
*pad_stepping = 16; *pad_stepping = 16;
return icelake_pch_h_communities; return icelake_pch_h_communities;
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
*community_count = ARRAY_SIZE(tigerlake_pch_lp_communities);
*pad_stepping = 16;
return tigerlake_pch_lp_communities;
case PCI_DEVICE_ID_INTEL_Q570:
case PCI_DEVICE_ID_INTEL_Z590:
case PCI_DEVICE_ID_INTEL_H570:
case PCI_DEVICE_ID_INTEL_B560:
case PCI_DEVICE_ID_INTEL_H510:
case PCI_DEVICE_ID_INTEL_WM590:
case PCI_DEVICE_ID_INTEL_QM580:
case PCI_DEVICE_ID_INTEL_HM570:
case PCI_DEVICE_ID_INTEL_C252:
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
*community_count = ARRAY_SIZE(tigerlake_pch_h_communities);
*pad_stepping = 16;
return tigerlake_pch_h_communities;
default: default:
return NULL; return NULL;
} }

1371
util/inteltool/gpio_names/tigerlake.h Normal file
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File diff suppressed because it is too large Load Diff

47
util/inteltool/inteltool.c
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@ -146,6 +146,20 @@ static const struct {
"Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" }, "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
"Xeon Scalable Processor 4th generation (Sapphire Rapids SP)" }, "Xeon Scalable Processor 4th generation (Sapphire Rapids SP)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2,
"11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4,
"11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2,
"11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4,
"11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4,
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6,
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8,
"11th generation (Tiger Lake H family) Core Processor (Mobile)" },
/* Southbridges (LPC controllers) */ /* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
@ -267,6 +281,16 @@ static const struct {
"Comet Point-LP U Premium/Cometlake" }, "Comet Point-LP U Premium/Cometlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE,
"Comet Point-LP U Base/Cometlake" }, "Comet Point-LP U Base/Cometlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER,
"Tiger Point U Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM,
"Tiger Point U Premium/Tigerlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE,
"Tiger Point U Base/Tigerlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER,
"Tiger Point Y Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM,
"Tiger Point Y Premium/Tigerlake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" },
@ -331,6 +355,17 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W580, "W580" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C256, "C256" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C252, "C252" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM570, "HM570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM580, "QM580" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM590, "WM590" },
/* Intel GPUs */ /* Intel GPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
"Intel(R) G35 Express Chipset Family" }, "Intel(R) G35 Express Chipset Family" },
@ -464,6 +499,18 @@ static const struct {
"Intel(R) Iris Plus Graphics 655" }, "Intel(R) Iris Plus Graphics 655" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7,
"Intel(R) Iris Plus Graphics G7" }, "Intel(R) Iris Plus Graphics G7" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_UY,
"Intel(R) Iris Xe Graphics" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_Y,
"Intel(R) Iris Xe Graphics" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1_2,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2,
"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS,
"Intel(R) UHD Graphics" }, "Intel(R) UHD Graphics" },
}; };

30
util/inteltool/inteltool.h
View File

@ -149,6 +149,11 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84
#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284
#define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086
#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087
#define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_H170 0xa144
#define PCI_DEVICE_ID_INTEL_Z170 0xa145 #define PCI_DEVICE_ID_INTEL_Z170 0xa145
@ -206,6 +211,18 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_HM370 0xa30d #define PCI_DEVICE_ID_INTEL_HM370 0xa30d
#define PCI_DEVICE_ID_INTEL_CM246 0xa30e #define PCI_DEVICE_ID_INTEL_CM246 0xa30e
#define PCI_DEVICE_ID_INTEL_Q570 0x4384
#define PCI_DEVICE_ID_INTEL_Z590 0x4385
#define PCI_DEVICE_ID_INTEL_H570 0x4386
#define PCI_DEVICE_ID_INTEL_B560 0x4387
#define PCI_DEVICE_ID_INTEL_H510 0x4388
#define PCI_DEVICE_ID_INTEL_WM590 0x4389
#define PCI_DEVICE_ID_INTEL_QM580 0x438a
#define PCI_DEVICE_ID_INTEL_HM570 0x438b
#define PCI_DEVICE_ID_INTEL_C252 0x438c
#define PCI_DEVICE_ID_INTEL_C256 0x438d
#define PCI_DEVICE_ID_INTEL_W580 0x438f
#define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
@ -310,6 +327,13 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */
#define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */ #define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */
#define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */ #define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */
@ -382,6 +406,12 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5
#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
#define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41 #define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41
#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40
#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49
#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60
#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78
#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70
#if !defined(__DARWIN__) && !defined(__FreeBSD__) #if !defined(__DARWIN__) && !defined(__FreeBSD__)
typedef struct { uint32_t hi, lo; } msr_t; typedef struct { uint32_t hi, lo; } msr_t;

16
util/inteltool/pcr.c
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@ -129,10 +129,26 @@ void pcr_init(struct pci_dev *const sb)
case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246: case PCI_DEVICE_ID_INTEL_CM246:
case PCI_DEVICE_ID_INTEL_Q570:
case PCI_DEVICE_ID_INTEL_Z590:
case PCI_DEVICE_ID_INTEL_H570:
case PCI_DEVICE_ID_INTEL_B560:
case PCI_DEVICE_ID_INTEL_H510:
case PCI_DEVICE_ID_INTEL_WM590:
case PCI_DEVICE_ID_INTEL_QM580:
case PCI_DEVICE_ID_INTEL_HM570:
case PCI_DEVICE_ID_INTEL_C252:
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
sbbar_phys = 0xfd000000; sbbar_phys = 0xfd000000;
use_p2sb = false; use_p2sb = false;
break; break;