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soc/intel/icelake: Make static IRQ mapping for PIC mode 

This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.

Change-Id: I9693f2a52529961e6b611b69e389f01f77f77d63
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Subrata Banik 2018-11-14 15:50:03 +05:30
parent 990db2213f
commit 8ad5a62de9
2 changed files with 13 additions and 24 deletions
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11
src/soc/intel/icelake/chip.h
View File

@ -34,17 +34,6 @@ struct soc_intel_icelake_config {
/* Common struct containing soc config data required by common code */ /* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config; struct soc_intel_common_config common_soc_config;
/* Interrupt Routing configuration.
* If bit7 is 1, the interrupt is disabled. */
uint8_t pirqa_routing;
uint8_t pirqb_routing;
uint8_t pirqc_routing;
uint8_t pirqd_routing;
uint8_t pirqe_routing;
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
/* GPE configuration */ /* GPE configuration */
uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ uint32_t gpe0_en_2; /* GPE0_EN_63_32 */

26
src/soc/intel/icelake/lpc.c
View File

@ -28,6 +28,7 @@
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <reg_script.h> #include <reg_script.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/lpc.h> #include <soc/lpc.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
@ -143,17 +144,16 @@ static void pch_enable_ioapic(const struct device *dev)
void soc_pch_pirq_init(const struct device *dev) void soc_pch_pirq_init(const struct device *dev)
{ {
const config_t *config = dev->chip_info;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
pch_interrupt_routing[0] = config->pirqa_routing; pch_interrupt_routing[0] = PCH_IRQ11;
pch_interrupt_routing[1] = config->pirqb_routing; pch_interrupt_routing[1] = PCH_IRQ10;
pch_interrupt_routing[2] = config->pirqc_routing; pch_interrupt_routing[2] = PCH_IRQ11;
pch_interrupt_routing[3] = config->pirqd_routing; pch_interrupt_routing[3] = PCH_IRQ11;
pch_interrupt_routing[4] = config->pirqe_routing; pch_interrupt_routing[4] = PCH_IRQ11;
pch_interrupt_routing[5] = config->pirqf_routing; pch_interrupt_routing[5] = PCH_IRQ11;
pch_interrupt_routing[6] = config->pirqg_routing; pch_interrupt_routing[6] = PCH_IRQ11;
pch_interrupt_routing[7] = config->pirqh_routing; pch_interrupt_routing[7] = PCH_IRQ11;
itss_irq_init(pch_interrupt_routing); itss_irq_init(pch_interrupt_routing);
#if defined(__SIMPLE_DEVICE__) #if defined(__SIMPLE_DEVICE__)
@ -171,16 +171,16 @@ void soc_pch_pirq_init(const struct device *dev)
switch (int_pin) { switch (int_pin) {
case 1: /* INTA# */ case 1: /* INTA# */
int_line = config->pirqa_routing; int_line = PCH_IRQ11;
break; break;
case 2: /* INTB# */ case 2: /* INTB# */
int_line = config->pirqb_routing; int_line = PCH_IRQ10;
break; break;
case 3: /* INTC# */ case 3: /* INTC# */
int_line = config->pirqc_routing; int_line = PCH_IRQ11;
break; break;
case 4: /* INTD# */ case 4: /* INTD# */
int_line = config->pirqd_routing; int_line = PCH_IRQ11;
break; break;
} }