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tpm: acpi: Add support for TPM PIRQ 

With SPI TPMs there is no SERIRQ for interrupts, instead it is
a PIRQ based interrupt.  The TCG PC Client Platform TPM Profile
Specification says it must be active low and shared.

This can be enabled with the CONFIG_TPM_PIRQ option that will
specify the interrupt vector to report for the TPM.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=verify TPM interrupt functionality in /proc/interrupts on glados

Change-Id: Iad3ced213d1fc5380c559f50c086206dc9f22534
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abdd0b8ecdf51ff32ed8bfee0823bbc30d5d3d49
Original-Change-Id: If7d22dfcfcab95dbd4c9edbd8674fc8d948a62d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304133
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12147
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-10-06 10:51:10 -07:00 committed by Patrick Georgi
parent d0def39413
commit 8b11b2c4df
2 changed files with 30 additions and 8 deletions
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8
src/drivers/pc80/tpm/Kconfig
View File

@ -23,6 +23,14 @@ config TPM_TIS_BASE_ADDRESS
Interface Specification 1.2 and should not be changed unless Interface Specification 1.2 and should not be changed unless
the TPM being used does not conform to TPM TIS 1.2. the TPM being used does not conform to TPM TIS 1.2.
config TPM_PIRQ
hex
default 0
depends on LPC_TPM
help
This can be used to specify a PIRQ to use instead of SERIRQ,
which is needed for SPI TPM interrupt support on x86.
config TPM_INIT_FAILURE_IS_FATAL config TPM_INIT_FAILURE_IS_FATAL
bool bool
default n default n

24
src/drivers/pc80/tpm/acpi/tpm.asl
View File

@ -63,16 +63,30 @@ Device (TPM)
IVEC, 4, /* SERIRQ vector */ IVEC, 4, /* SERIRQ vector */
} }
If (LGreater (IVEC, 0)) {
/* Update interrupt vector */
CreateField (^IBUF, ^TIRQ._INT, 32, TVEC) CreateField (^IBUF, ^TIRQ._INT, 32, TVEC)
Store (IVEC, TVEC)
/* Update interrupt type and polarity */
CreateBitField (^IBUF, ^TIRQ._HE, TTYP) CreateBitField (^IBUF, ^TIRQ._HE, TTYP)
CreateBitField (^IBUF, ^TIRQ._LL, TPOL) CreateBitField (^IBUF, ^TIRQ._LL, TPOL)
CreateBitField (^IBUF, ^TIRQ._SHR, TSHR) CreateBitField (^IBUF, ^TIRQ._SHR, TSHR)
If (LGreater (CONFIG_TPM_PIRQ, 0)) {
/*
* PIRQ: Update interrupt vector with configured PIRQ
*/
Store (CONFIG_TPM_PIRQ, TVEC)
/* Active-Low Level-Triggered Shared */
Store (One, TPOL)
Store (Zero, TTYP)
Store (One, TSHR)
/* Merge IRQ with base address */
Return (ConcatenateResTemplate (RBUF, IBUF))
} ElseIf (LGreater (IVEC, 0)) {
/*
* SERIRQ: Update interrupt vector based on TPM register
*/
Store (IVEC, TVEC)
If (LEqual (ITPL, 0x0)) { If (LEqual (ITPL, 0x0)) {
/* Active-High Level-Triggered Shared */ /* Active-High Level-Triggered Shared */
Store (Zero, TPOL) Store (Zero, TPOL)