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sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: I212ef304a03d068232f50a71c318e2b468336339
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-04-28 09:58:21 +02:00 committed by Patrick Georgi
parent 7b2646536a
commit 8b6dfdeb20
4 changed files with 15 additions and 20 deletions
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3
src/southbridge/intel/ibexpeak/azalia.c
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@ -262,8 +262,7 @@ static void azalia_init(struct device *dev)
pci_write_config32(dev, 0xd0, reg32); pci_write_config32(dev, 0xd0, reg32);
/* Set Bus Master */ /* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused? pci_write_config8(dev, 0x3c, 0x0a); // unused?

15
src/southbridge/intel/ibexpeak/me.c
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@ -358,6 +358,7 @@ static void intel_me7_finalize_smm(void)
{ {
struct me_hfs hfs; struct me_hfs hfs;
u32 reg32; u32 reg32;
u16 reg16;
mei_base_address = (u32 *) mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@ -380,10 +381,10 @@ static void intel_me7_finalize_smm(void)
mkhi_end_of_post(); mkhi_end_of_post();
/* Make sure IO is disabled */ /* Make sure IO is disabled */
reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
/* Hide the PCI device */ /* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1); RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@ -475,7 +476,7 @@ static int intel_mei_setup(struct device *dev)
{ {
struct resource *res; struct resource *res;
struct mei_csr host; struct mei_csr host;
u32 reg32; u16 reg16;
/* Find the MMIO base for the ME interface */ /* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -486,9 +487,9 @@ static int intel_mei_setup(struct device *dev)
mei_base_address = (u32 *)(uintptr_t)res->base; mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */ /* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Clean up status for next message */ /* Clean up status for next message */
read_host_csr(&host); read_host_csr(&host);

12
src/southbridge/intel/ibexpeak/pch.c
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@ -66,24 +66,22 @@ static void pch_disable_devfn(struct device *dev)
void pch_enable(struct device *dev) void pch_enable(struct device *dev)
{ {
u32 reg32; u16 reg16;
if (!dev->enabled) { if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable this device if possible */ /* Disable this device if possible */
pch_disable_devfn(dev); pch_disable_devfn(dev);
} else { } else {
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
} }
} }

5
src/southbridge/intel/ibexpeak/usb_ehci.c
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@ -30,10 +30,7 @@ static void usb_ehci_init(struct device *dev)
pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xf4, 0x00808588);
pci_write_config32(dev, 0xfc, 0x301b1728); pci_write_config32(dev, 0xfc, 0x301b1728);
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg32 |= PCI_COMMAND_MASTER;
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
access_cntl = pci_read_config8(dev, 0x80); access_cntl = pci_read_config8(dev, 0x80);