mb/google/brya/brya0: Update GPIO tables based on new board rev

This change also restores GPIOs to their proper settings for prior board
revs.

BUG=b:189362981

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/baseboard/gpio.c

@@ -26,7 +26,7 @@ static const struct pad_config gpio_table[] = {
 	/* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
 	/* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */
 	PAD_CFG_GPO(GPP_A11, 1, DEEP),
-	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
+	/* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
 	PAD_CFG_GPO(GPP_A12, 1, DEEP),
 	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
@@ -55,8 +55,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
 	/* B1  : SOC_VID1 */
 	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
-	/* B2  : VRALERT# ==> NC */
+	/* B2  : VRALERT# ==> M2_SSD_PLA_L */
-	PAD_NC(GPP_B2, NONE),
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
 	/* B3  : PROC_GP2 ==> SAR2_INT_L */
 	PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL),
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
@@ -81,8 +81,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14 : SPKR ==> GPP_B14_STRAP */
 	PAD_NC(GPP_B14, NONE),
-	/* B15 : TIME_SYNC0 ==> NC */
+	/* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
-	PAD_NC(GPP_B15, NONE),
+	PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
 	/* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
 	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
 	/* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
@@ -106,10 +106,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_C1, 0, DEEP),
 	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
 	PAD_NC(GPP_C2, NONE),
-	/* C3  : SML0CLK ==> NC */
+	/* C3 : SML0CLK ==> EN_UCAM_PWR */
-	PAD_NC(GPP_C3, NONE),
+	PAD_CFG_GPO(GPP_C3, 0, DEEP),
-	/* C4  : SML0DATA ==> NC */
+	/* C4 : SML0DATA ==> EN_UCAM_SENR_PWR */
-	PAD_NC(GPP_C4, NONE),
+	PAD_CFG_GPO(GPP_C4, 0, DEEP),
 	/* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
 	PAD_NC(GPP_C5, NONE),
 	/* C6  : SML1CLK ==> USI_REPORT_EN */
@@ -143,10 +143,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_D11, 1, DEEP),
 	/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
 	PAD_NC(GPP_D12, NONE),
-	/* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
+	/* D13 : ISH_UART0_RXD ==> CAM_PSW_L */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
+	PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, EDGE_BOTH),
-	/* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
+	/* D14 : ISH_UART0_TXD ==> SPKR_INT_L */
-	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
+	PAD_CFG_GPI(GPP_D14, NONE, DEEP),
 	/* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
 	PAD_CFG_GPO(GPP_D15, 0, DEEP),
 	/* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
@@ -245,12 +245,12 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT),
 	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
-	/* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
+	/* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */
-	PAD_CFG_GPI(GPP_F19, NONE, DEEP),
+	PAD_CFG_GPO(GPP_F19, 1, PLTRST),
-	/* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
+	/* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */
 	PAD_CFG_GPO(GPP_F20, 0, DEEP),
-	/* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_F21, NONE, DEEP, LEVEL, INVERT),
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 	/* F22 : NC */
 	PAD_NC(GPP_F22, NONE),
 	/* F23 : NC */
@@ -298,8 +298,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
 	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_H20, 1, DEEP),
-	/* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
+	/* H21 : IMGCLKOUT2 ==>  UCAM_MCLK */
-	PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
 	/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
 	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
 	/* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */
@@ -343,8 +343,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 	/* GPD1: ACPRESENT ==> PCH_ACPRESENT */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
-	/* GPD2: LAN_WAKE# ==> NC */
+	/* GPD2 : LAN_WAKE# ==> EC_PCH_WAKE_ODL */
-	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 	/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
 	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 	/* GPD4: SLP_S3# ==> SLP_S3_L */

src/mainboard/google/brya/variants/brya0/Makefile.inc

@@ -1 +1,3 @@
+bootblock-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += gpio.c

src/mainboard/google/brya/variants/brya0/gpio.c

@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <string.h>
+
+static const struct pad_config board_id0_1_overrides[] = {
+	/* B2  : VRALERT# ==> NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B15 : TIME_SYNC0 ==> NC */
+	PAD_NC(GPP_B15, NONE),
+	/* C3  : SML0CLK ==> NC */
+	PAD_NC(GPP_C3, NONE),
+	/* C4  : SML0DATA ==> NC */
+	PAD_NC(GPP_C4, NONE),
+	/* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
+	/* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
+	/* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
+	PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
+	/* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
+	PAD_NC(GPP_F21, NONE),
+	/* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
+	PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
+	/* GPD2: LAN_WAKE# ==> NC */
+	PAD_NC(GPD2, NONE),
+};
+
+/* Early pad configuration in bootblock for board id < 2 */
+static const struct pad_config early_gpio_table[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> NC */
+	PAD_NC(GPP_F21, NONE),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+/* Early pad configuration in bootblock for board id 2 */
+static const struct pad_config early_gpio_table_id2[] = {
+	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/*
+	 * D1  : ISH_GP1 ==> FP_RST_ODL
+	 * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
+	 * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
+	 * early on in bootblock, followed by enabling of power. Reset signal is deasserted
+	 * later on in ramstage. Since reset signal is asserted in bootblock, it results in
+	 * FPMCU not working after a S3 resume. This is a known issue.
+	 */
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	/* D2  : ISH_GP2 ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* E0  : SATAXPCIE0 ==> WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+	/* E16 : RSVD_TP ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	/* E15 : RSVD_TP ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated below) */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
+	PAD_NC(GPP_H13, UP_20K),
+};
+
+const struct pad_config *variant_gpio_override_table(size_t *num)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(board_id0_1_overrides);
+		return board_id0_1_overrides;
+	}
+
+	*num = 0;
+	return NULL;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	const uint32_t id = board_id();
+	if (id == BOARD_ID_UNKNOWN || id < 2) {
+		*num = ARRAY_SIZE(early_gpio_table);
+		return early_gpio_table;
+	}
+
+	*num = ARRAY_SIZE(early_gpio_table_id2);
+	return early_gpio_table_id2;
+}