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mb/intel/adlrvp_m: Configure DP_HPD as PAD_NC and disable DdiPortHpd 

GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Bernardo Perez Priego 2021-06-15 17:26:31 -07:00 committed by Felix Held
parent e4aa07e2bd
commit b10afbd2e2
2 changed files with 7 additions and 1 deletions
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4
src/mainboard/intel/adlrvp/devicetree_m.cb
View File

@ -86,6 +86,10 @@ chip soc/intel/alderlake
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# Disable DDI ports HPD
register "DdiPort1Hpd" = "0"
register "DdiPort2Hpd" = "0"
# TCSS USB3
register "TcssAuxOri" = "0"

4
src/mainboard/intel/adlrvp/gpio_m.c
View File

@ -110,7 +110,9 @@ static const struct pad_config gpio_table[] = {
/* HPD_1 (E14) and HPD_2 (A18) pins */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
/* GPIO pin for PCIE SRCCLKREQB */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),