nb/intel/sandybridge: Deduplicate PCIEXBAR decoding
We can use `decode_pcie_bar` instead, as other northbridges do. Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -11,48 +11,19 @@
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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int max_buses;
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u32 length, pciexbar;
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struct device *const dev = pcidev_on_root(0, 0);
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if (!dev)
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if (!decode_pcie_bar(&pciexbar, &length))
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return current;
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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/* MMCFG not supported or not enabled */
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if (!(pciexbar_reg & (1 << 0)))
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return current;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: /* 256MB */
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pciexbar = pciexbar_reg & (0xffffffffULL << 28);
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max_buses = 256;
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break;
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case 1: /* 128M */
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pciexbar = pciexbar_reg & (0xffffffffULL << 27);
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max_buses = 128;
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break;
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case 2: /* 64M */
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pciexbar = pciexbar_reg & (0xffffffffULL << 26);
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max_buses = 64;
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break;
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default: /* RSVD */
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return current;
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}
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if (!pciexbar)
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return current;
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const int max_buses = length / MiB;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
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max_buses - 1);
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max_buses - 1);
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return current;
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}
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static unsigned long acpi_create_igfx_rmrr(const unsigned long current)
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{
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const u32 base_mask = ~(u32)(MiB - 1);
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@ -40,7 +40,7 @@ int bridge_silicon_revision(void)
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static const int legacy_hole_size_k = 384;
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static int decode_pcie_bar(u32 *const base, u32 *const len)
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int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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*base = 0;
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*len = 0;
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@ -177,6 +177,8 @@ void perform_raminit(int s3resume);
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void report_memory_config(void);
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enum platform_type get_platform_type(void);
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int decode_pcie_bar(u32 *const base, u32 *const len);
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#include <device/device.h>
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struct acpi_rsdp;
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