mainboard/opencellular/elgon: Add mainboard support

Tested on Elgon EVT board and boots into GNU/Linux.

TODO:
* Add hard reset function for VBOOT.
* Add EC code
* Add SPI flash write protection

Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Philipp Deppenwiese 2018-08-10 16:15:14 -07:00 committed by Philipp Deppenwiese
parent 7de4bb5172
commit 8c678cf46a
19 changed files with 1346 additions and 0 deletions

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@ -18,6 +18,10 @@ This section contains documentation about coreboot on specific mainboards.
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
## Open Cellular
- [Elgon](opencellular/elgon.md)
## HP
- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)

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# Elgon
This page describes how to run coreboot on the [Elgon] compute board
from [OpenCellular].
## TODO
* Add hard reset control
## Flashing coreboot
```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Model | W25Q128 |
+---------------------+------------+
| Size | 16 MiB |
+---------------------+------------+
| In circuit flashing | yes |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Write protection | No |
+---------------------+------------+
| Dual BIOS feature | No |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
```
### Internal programming
The SPI flash can be accessed using [flashrom].
### External programming
The EVT board does have a pinheader to flash the SOIC-8 in circuit.
Directly connecting a Pomona test-clip on the flash is also possible.
TODO: pinout
**Total board view of EVT**
![][elgon1]
[elgon1]: elgon1.png
**Closeup view of SOIC-8 flash IC, programming pin header and
USB serial connector of EVT**
![][elgon2]
[elgon2]: elgon2.png
## Technology
```eval_rst
+---------------+----------------------------------------+
| SoC | :doc:`../../soc/cavium/cn81xx/index` |
+---------------+----------------------------------------+
| CPU | Cavium ARMv8-Quadcore `CN81XX`_ |
+---------------+----------------------------------------+
.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
```
[Elgon]: https://github.com/Telecominfraproject/OpenCellular
[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
[flashrom]: https://flashrom.org/Flashrom

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##
## This file is part of the coreboot project.
##
## Copyright 2018 Facebook, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_OPENCELLULAR_ELGON
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select COMMON_CBFS_SPI_WRAPPER
select RTC
select SOC_CAVIUM_CN81XX
select SPI_FLASH
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_I2C_TPM_GENERIC
select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_NO_BOARD_SUPPORT
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
config GBB_HWID
string
depends on VBOOT
default "ELGON"
config MAINBOARD_DIR
string
default "opencellular/elgon"
config DRIVER_TPM_I2C_BUS
hex
default 0x1
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config DRAM_SIZE_MB
int
default 4096
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 0
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0x87E028000000
config UART_FOR_CONSOLE
int
depends on DRIVERS_UART
default 0
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot.fmd" if VBOOT
config MAX_CPUS
default 4
##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
config DEVICETREE
string
default "devicetree.cb"
config MAINBOARD_PART_NUMBER
string
default "Elgon"
config MAINBOARD_FIT_DTS
string
default "gbcv2.dts"
endif

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config BOARD_OPENCELLULAR_ELGON
bool "Elgon (GBCv2)"

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##
## This file is part of the coreboot project.
##
## Copyright 2017-present Facebook, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
bootblock-y += bootblock.c
bootblock-y += memlayout.ld
bootblock-y += death.c
romstage-y += memlayout.ld
romstage-y += romstage.c
romstage-y += bdk_devicetree.c
romstage-y += death.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += bdk_devicetree.c
ramstage-y += death.c
verstage-y += memlayout.ld
verstage-y += death.c

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@ -0,0 +1,106 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017-present Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
// This file is automatically generated.
// DO NOT EDIT BY HAND.
#include <bdk-devicetree.h>
const struct bdk_devicetree_key_value devtree[] = {
{"DDR-CONFIG-DQX-CTL", "0x4"},
{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},
{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"},
{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"},
{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"},
{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"},
{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"},
{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"},
{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"},
{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"},
{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"},
{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"},
{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"},
{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"},
{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"},
{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"},
{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"},
{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"},
{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"},
{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"},
{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"},
{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"},
{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"},
{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"},
{"PHY-ADDRESS.N0.BGX0.P0", "0x00001000"},
{"PHY-ADDRESS.N0.BGX2.P0", "0x00001000"},
{"BGX-ENABLE.N0.BGX0.P0", "1"},
{"BGX-ENABLE.N0.BGX0.P1", "0"},
{"BGX-ENABLE.N0.BGX0.P2", "0"},
{"BGX-ENABLE.N0.BGX0.P3", "0"},
{"BGX-ENABLE.N0.BGX1.P0", "0"},
{"BGX-ENABLE.N0.BGX1.P1", "0"},
{"BGX-ENABLE.N0.BGX2.P0", "1"},
{"BDK-NUM-PACKET-BUFFERS", "0x1000"},
{"BDK-PACKET-BUFFER-SIZE", "0x400"},
{"BDK-SHOW-LINK-STATUS", "1"},
{"BDK-COREMASK", "0"},
{"BDK-BOOT-MENU-TIMEOUT", "0x05"},
{"BDK-BOOT-PATH-OPTION", "0"},
{"BDK-CONFIG-TRACE", "1"},
{"MULTI-NODE", "0"},
{"QLM-AUTO-CONFIG", "0"},
{"QLM-DIP-AUTO-CONFIG", "0"},
{"QLM-MODE.N0.QLM0", "PCIE_1X1"},
{"QLM-MODE.N0.QLM1", "SGMII_2X1"},
{"QLM-MODE.N0.QLM2", "PCIE_1X2"},
{"QLM-MODE.N0.QLM3", "SATA_2X1"},
{"QLM-FREQ.N0.QLM0", "6000"},
{"QLM-FREQ.N0.QLM1", "1250"},
{"QLM-FREQ.N0.QLM2", "6000"},
{"QLM-FREQ.N0.QLM3", "6000"},
{"QLM-CLK.N0.QLM0", "2"},
{"QLM-CLK.N0.QLM1", "2"},
{"QLM-CLK.N0.QLM2", "2"},
{"QLM-CLK.N0.QLM3", "2"},
{"DDR-SPEED.N0", "1600"},
{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"},
{"USB-REFCLK-SRC.N0.PORT0", "0"},
{"GPIO-PIN-SELECT-GPIO45", "0x2"},
{"GPIO-PIN-SELECT-GPIO46", "0x250"},
{0, 0},
};

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@ -0,0 +1,15 @@
FLASH@0x0 16M {
WP_RO@0x0 0x1000000 {
RO_SECTION@0x0 0xffc000 {
# 0 - 0x10000 is free for firmware usage.
# bootblock starts at 0x20000
FMAP@0x0 0x1000
# bootblock includes trusted/non-trusted CLIB, CSIB,
# and BL1FWs packaged in
# src/soc/cavium/common/Makefile.inc.
BOOTBLOCK@0x10000 0x70000
COREBOOT(CBFS)@0x80000 0xf7c000
}
RO_VPD@0xffc000 0x4000
}
}

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Vendor name: Open Cellular
Board name: Elgon
Category: sbc
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

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/*
* This file is part of the coreboot project.
*
* Copyright 2018 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <soc/soc.h>
#include <soc/spi.h>
#include <soc/uart.h>
#include <soc/gpio.h>
#include "mainboard.h"
void bootblock_mainboard_early_init(void)
{
/* Route UART0 to CON1 */
gpio_output(ELGON_GPIO_UART_SEL, 0);
/* Turn off error LED */
gpio_output(ELGON_GPIO_ERROR_LED, 0);
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))
uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);
}
}
static void configure_spi_flash(void)
{
/* The maximum SPI frequency for error free transmission is at 30 Mhz */
spi_init_custom(0, // bus
28000000, // speed Hz
0, // idle low disabled
0, // zero idle cycles between transfers
0, // MSB first
0, // Chip select 0
1); // assert is high
/* Route SPI to SoC */
gpio_output(ELGON_GPIO_SPI_MUX, 1);
}
void bootblock_mainboard_init(void)
{
configure_spi_flash();
// FIXME: Check SPI flash WP bits
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2017-present Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <soc/gpio.h>
#include <console/console.h>
#include <delay.h>
#include "mainboard.h"
void die_notify(void)
{
const u32 rate = 1000 / 10; // blink at 5 Hz
do {
gpio_output(ELGON_GPIO_ERROR_LED, 0);
mdelay(rate);
gpio_output(ELGON_GPIO_ERROR_LED, 1);
mdelay(rate);
} while (1);
}

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##
## This file is part of the coreboot project.
##
## Copyright 2017-present Facebook, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip soc/cavium/cn81xx
device cpu_cluster 0 on end
device domain 0 on
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.0 on # PCI bridge
chip soc/cavium/common/pci
register "secure" = "0"
device pci 00.0 on end # MRML
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 00.1 on end # RESET
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 00.2 on end # DAP
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 00.3 on end # MDIO
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 00.4 on end # FUSE
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.2 on end # SGPIO
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.3 on end # SMI
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.4 on end # MMC
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 01.5 on end # KEY
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 01.6 on end # BOOT BUS
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 01.7 on end # PBUS
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 02.0 on end # XCV
end
device pci 04.0 on end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 06.0 on end # L2C-TAD
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 07.0 on end # L2C-CBC
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 07.4 on end # L2C-MCI
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.0 on end # UUA0
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.1 on end # UUA1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.2 off end # UUA2
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.3 off end # UUA3
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 08.4 on end # VRM
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 09.0 on end # I2C0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 09.1 on end # I2C1
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 0a.0 on end # PCC Bridge
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0b.0 on end # IOBN
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 0c.0 on end # OCLA0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 0c.1 on end # OCLA1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0d.0 on end
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0e.0 on end # PCIe0
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0e.1 on end # PCIe1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 0e.2 on end # PCIe2
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 10.0 on end # bgx0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 10.1 off end # bgx1
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 11.0 on end # rgx0
end
chip soc/cavium/common/pci
register "secure" = "0"
device pci 12.0 on end # MAC
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.0 on end # GSER0
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.1 on end # GSER1
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.2 on end # GSER2
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 1c.3 on end # GSER3
end
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 02.0 on end #SMMU
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 03.0 on end #GIC
end
chip soc/cavium/common/pci
register "secure" = "1"
device pci 04.0 on end #GTI
end
device pci 05.0 on end # NIC
device pci 06.0 on end # GPIO
device pci 07.0 on end # SPI
device pci 08.0 on end # MIO
device pci 09.0 on end # PCI bridge
device pci 0a.0 on end # PCI bridge
device pci 0b.0 on end # NFC
device pci 0c.0 on end # PCI bridge
device pci 0d.0 on end # PCM
device pci 0e.0 on end # VRM
device pci 0f.0 on end # PCI bridge
device pci 10.0 on end # USB0
device pci 11.0 on end # USB1
device pci 16.0 on end # SATA0
device pci 17.0 on end # SATA1
end
end
end

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/*
* This file is part of the coreboot project.
*
* Copyright 2018 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/ {
model = "Cavium ThunderX CN81XX board";
compatible = "cavium,thunder-81xx";
interrupt-parent = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu-map {
cluster0 {
core0 {
cpu = <0x2>;
};
core1 {
cpu = <0x3>;
};
core2 {
cpu = <0x4>;
};
core3 {
cpu = <0x5>;
};
};
};
cpu@0 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
numa-node-id = <0x0>;
next-level-cache = <0x6>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
cpu@1 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
numa-node-id = <0x0>;
next-level-cache = <0x6>;
linux,phandle = <0x3>;
phandle = <0x3>;
};
cpu@2 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
numa-node-id = <0x0>;
next-level-cache = <0x6>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
cpu@3 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
numa-node-id = <0x0>;
next-level-cache = <0x6>;
linux,phandle = <0x5>;
phandle = <0x5>;
};
};
l2-cache0 {
compatible = "cache";
numa-node-id = <0x0>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x1 0xd 0x4 0x1 0xe 0x4 0x1 0xb 0x4 0x1 0xa 0x4>;
};
pmu {
compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
interrupts = <0x1 0x7 0x4>;
};
mmc_supply_3v3 {
compatible = "regulator-fixed";
regulator-name = "mmc_supply_3v3";
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
gpio = <0x7 0x8 0x0>;
enable-active-high;
linux,phandle = <0xf>;
phandle = <0xf>;
};
interrupt-controller@801000000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x3>;
#address-cells = <0x2>;
#size-cells = <0x2>;
#redistributor-regions = <0x1>;
ranges;
interrupt-controller;
reg = <0x8010 0x0 0x0 0x10000 0x8010 0x80000000 0x0 0x600000>;
interrupts = <0x1 0x9 0x4>;
linux,phandle = <0x1>;
phandle = <0x1>;
gic-its@801000020000 {
compatible = "arm,gic-v3-its";
reg = <0x8010 0x20000 0x0 0x200000>;
msi-controller;
numa-node-id = <0x0>;
linux,phandle = <0xd>;
phandle = <0xd>;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
numa-node-id = <0x0>;
refclkuaa {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x6f3c900>;
clock-output-names = "refclkuaa";
linux,phandle = <0x8>;
phandle = <0x8>;
};
sclk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <0x2faf0800>;
clock-output-names = "sclk";
linux,phandle = <0xe>;
phandle = <0xe>;
};
serial@87e028000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x28000000 0x0 0x1000>;
interrupts = <0x0 0x5 0x4>;
clocks = <0x8>;
clock-names = "apb_pclk";
skip-init;
};
serial@87e029000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x29000000 0x0 0x1000>;
interrupts = <0x0 0x6 0x4>;
clocks = <0x8>;
clock-names = "apb_pclk";
skip-init;
};
serial@87e02a000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x2a000000 0x0 0x1000>;
interrupts = <0x0 0x7 0x4>;
clocks = <0x8>;
clock-names = "apb_pclk";
skip-init;
};
serial@87e02b000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x2b000000 0x0 0x1000>;
interrupts = <0x0 0x8 0x4>;
clocks = <0x8>;
clock-names = "apb_pclk";
skip-init;
};
watch-dog@8440000a0000 {
compatible = "arm,sbsa-gwdt";
reg = <0x8440 0xa0000 0x0 0x1000 0x8440 0xb0000 0x0 0x1000>;
interrupts = <0x0 0x9 0x4>;
};
smmu0@830000000000 {
compatible = "cavium,smmu-v2";
reg = <0x8300 0x0 0x0 0x2000000>;
#global-interrupts = <0x1>;
interrupts = <0x0 0x44 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4 0x0 0x45 0x4>;
mmu-masters = <0x9 0x100 0xa 0x200 0xb 0x300 0xc 0x400>;
};
pci@848000000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
msi-parent = <0xd>;
msi-map = <0x0 0xd 0x0 0x10000>;
bus-range = <0x0 0x1f>;
#size-cells = <0x2>;
#address-cells = <0x3>;
#stream-id-cells = <0x1>;
dma-coherent;
reg = <0x8480 0x0 0x0 0x2000000>;
ranges = <0x3000000 0x8010 0x0 0x8010 0x0 0x80 0x0 0x3000000 0x8100 0x0 0x8100 0x0 0x80 0x0 0x3000000 0x8680 0x0 0x8680 0x0 0x160 0x28000000 0x3000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x0 0x94000000 0x3000000 0x8400 0x0 0x8400 0x0 0x10 0x0 0x3000000 0x8430 0x0 0x8430 0x0 0x2 0x0 0x3000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x1f 0x3a000000>;
linux,phandle = <0x9>;
phandle = <0x9>;
mrml-bridge0@1,0 {
compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge";
#size-cells = <0x2>;
#address-cells = <0x3>;
ranges = <0x3000000 0x87e0 0x0 0x3000000 0x87e0 0x0 0x10 0x0>;
reg = <0x800 0x0 0x0 0x0 0x0>;
device_type = "pci";
mdio-nexus@1,3 {
compatible = "cavium,thunder-8890-mdio-nexus";
#address-cells = <0x2>;
#size-cells = <0x2>;
reg = <0xb00 0x0 0x0 0x0 0x0>;
assigned-addresses = <0x3000000 0x87e0 0x5000000 0x0 0x800000>;
ranges = <0x87e0 0x5000000 0x3000000 0x87e0 0x5000000 0x0 0x800000>;
mdio0@87e005003800 {
compatible = "cavium,thunder-8890-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x87e0 0x5003800 0x0 0x30>;
};
mdio1@87e005003880 {
compatible = "cavium,thunder-8890-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x87e0 0x5003880 0x0 0x30>;
};
};
mmc@1,4 {
compatible = "cavium,thunder-8890-mmc";
reg = <0xc00 0x0 0x0 0x0 0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <0xe>;
mmc-slot@0 {
compatible = "mmc-slot";
reg = <0x0>;
vmmc-supply = <0xf>;
max-frequency = <0x18cba80>;
no-1-8-v;
bus-width = <0x4>;
disable-wp;
broken-cd;
sd-uhs-sdr25;
sd-uhs-ddr50;
sd-uhs-sdr50;
cap-sd-highspeed;
no-sdio;
no-mmc;
};
};
i2c@9,0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,thunder-8890-twsi";
reg = <0x4800 0x0 0x0 0x0 0x0>;
clock-frequency = <0x186a0>;
clocks = <0xe>;
idt-ptp@0x52 {
compatible = "idt,82p33914-1";
reg = <0x52>;
};
};
i2c@9,1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,thunder-8890-twsi";
reg = <0x4900 0x0 0x0 0x0 0x0>;
clock-frequency = <0x186a0>;
clocks = <0xe>;
rom@54 {
compatible = "atmel,24c256";
reg = <0x54>;
pagesize = <0x40>;
};
rtc@68 {
compatible = "isil,isl12057";
reg = <0x68>;
};
tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
};
};
rgx0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,thunder-8890-bgx";
reg = <0x9000 0x0 0x0 0x0 0x0>;
rgmii00 {
reg = <0x0>;
local-mac-address = [00 00 00 00 00 00];
};
};
bgx0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,thunder-8890-bgx";
reg = <0x8000 0x0 0x0 0x0 0x0>;
sgmii00 {
reg = <0x0>;
qlm-mode = "0x000,sgmii";
local-mac-address = [00 00 00 00 00 00];
cavium,disable-autonegotiation;
};
};
bgx1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,thunder-8890-bgx";
reg = <0x8100 0x0 0x0 0x0 0x0>;
};
};
spi@7,0 {
compatible = "cavium,thunder-8190-spi";
reg = <0x3800 0x0 0x0 0x0 0x0>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <0xe>;
flash@0 {
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <104000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
gpio0@6,0 {
#gpio-cells = <0x2>;
compatible = "cavium,thunder-8890-gpio";
gpio-controller;
reg = <0x3000 0x0 0x0 0x0 0x0>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
nand@b,0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,cn8130-nand";
reg = <0x5800 0x0 0x0 0x0 0x0>;
clocks = <0xe>;
};
};
pci@87e0c0000000 {
compatible = "cavium,pci-host-thunder-pem";
device_type = "pci";
msi-parent = <0xd>;
msi-map = <0x0 0xd 0x0 0x10000>;
bus-range = <0x1f 0x57>;
#size-cells = <0x2>;
#address-cells = <0x3>;
#stream-id-cells = <0x1>;
dma-coherent;
reg = <0x8800 0x1f000000 0x0 0x39000000 0x87e0 0xc0000000 0x0 0x1000000>;
ranges = <0x1000000 0x0 0x0 0x8830 0x0 0x0 0x10000 0x3000000 0x0 0x10000000 0x8810 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x8820 0x0 0x10 0x0 0x3000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x0 0x1000000>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x10 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x11 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x13 0x4>;
linux,phandle = <0xa>;
phandle = <0xa>;
};
pci@87e0c1000000 {
compatible = "cavium,pci-host-thunder-pem";
device_type = "pci";
msi-parent = <0xd>;
msi-map = <0x0 0xd 0x0 0x10000>;
bus-range = <0x57 0x8f>;
#size-cells = <0x2>;
#address-cells = <0x3>;
#stream-id-cells = <0x1>;
dma-coherent;
reg = <0x8840 0x57000000 0x0 0x39000000 0x87e0 0xc1000000 0x0 0x1000000>;
ranges = <0x1000000 0x0 0x10000 0x8870 0x10000 0x0 0x10000 0x3000000 0x0 0x10000000 0x8850 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x8860 0x0 0x10 0x0 0x3000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x0 0x1000000>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x14 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x15 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x16 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x17 0x4>;
linux,phandle = <0xb>;
phandle = <0xb>;
};
pci@87e0c2000000 {
compatible = "cavium,pci-host-thunder-pem";
device_type = "pci";
msi-parent = <0xd>;
msi-map = <0x0 0xd 0x0 0x10000>;
bus-range = <0x8f 0xc7>;
#size-cells = <0x2>;
#address-cells = <0x3>;
#stream-id-cells = <0x1>;
dma-coherent;
reg = <0x8880 0x8f000000 0x0 0x39000000 0x87e0 0xc2000000 0x0 0x1000000>;
ranges = <0x1000000 0x0 0x20000 0x88b0 0x20000 0x0 0x10000 0x3000000 0x0 0x10000000 0x8890 0x10000000 0xf 0xf0000000 0x43000000 0x10 0x0 0x88a0 0x0 0x10 0x0 0x3000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x0 0x1000000>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x18 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x19 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x1a 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x1b 0x4>;
linux,phandle = <0xc>;
phandle = <0xc>;
};
tdm@d,0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cavium,thunder-8190-tdm";
reg = <0x6800 0x0 0x0 0x0>;
clocks = <0xe>;
};
};
aliases {
serial0 = "/soc@0/serial@87e028000000";
serial1 = "/soc@0/serial@87e029000000";
serial2 = "/soc@0/serial@87e02a000000";
serial3 = "/soc@0/serial@87e02b000000";
i2c0 = "/soc@0/pci@848000000000/mrml-bridge0@1,0/i2c@9,0";
i2c1 = "/soc@0/pci@848000000000/mrml-bridge0@1,0/i2c@9,1";
spi0 = "/soc@0/pci@848000000000/spi@7,0";
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x1400000 0x0 0x7ec00000>;
numa-node-id = <0x0>;
};
};

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/*
* This file is part of the coreboot project.
*
* Copyright 2017-2018 Facebook, Inc.
* Copyright 2003-2017 Cavium Inc. (support@cavium.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
*/
#include <device/device.h>
#include <libbdk-hal/bdk-config.h>
#include <libbdk-hal/bdk-twsi.h>
#include <soc/gpio.h>
#include <delay.h>
#include <soc/uart.h>
#include <console/console.h>
#include <soc/clock.h>
#include <soc/gpio.h>
#include <soc/timer.h>
#include <soc/cpu.h>
#include <soc/sdram.h>
#include <soc/spi.h>
#include <spi_flash.h>
#include <fmap.h>
#include <libbdk-hal/bdk-config.h>
static void mainboard_print_info(void)
{
struct region region;
if (fmap_locate_area("WP_RO", &region) < 0) {
printk(BIOS_ERR, "MB: Could not find region '%s'\n", "WP_RO");
} else {
const struct spi_flash *flash = boot_device_spi_flash();
const bool prot = (flash != NULL) &&
(spi_flash_is_write_protected(flash, &region) == 1);
printk(BIOS_INFO, "MB: WP_RO is %swrite protected\n",
prot ? "" : "not ");
}
printk(BIOS_INFO, "MB: trusted boot : %s\n",
gpio_strap_value(10) ? "yes" : "no");
const size_t boot_method = gpio_strap_value(0) |
(gpio_strap_value(1) << 1) |
(gpio_strap_value(2) << 2) |
(gpio_strap_value(3) << 3);
printk(BIOS_INFO, "MB: boot method : ");
switch (boot_method) {
case 0x2:
case 0x3:
printk(BIOS_INFO, "EMMC\n");
break;
case 0x5:
case 0x6:
printk(BIOS_INFO, "SPI\n");
break;
case 0x8:
printk(BIOS_INFO, "REMOTE\n");
break;
case 0xc:
case 0xd:
printk(BIOS_INFO, "PCIe\n");
break;
default:
printk(BIOS_INFO, "unknown\n");
}
printk(BIOS_INFO, "MB: REFclk : %llu MHz\n",
thunderx_get_ref_clock() / 1000000ULL);
printk(BIOS_INFO, "MB: IOclk : %llu MHz\n",
thunderx_get_io_clock() / 1000000ULL);
printk(BIOS_INFO, "MB: COREclk : %llu MHz\n",
thunderx_get_core_clock() / 1000000ULL);
printk(BIOS_INFO, "MB: #CPU cores : %zu\n",
cpu_get_num_available_cores());
printk(BIOS_INFO, "MB: RAM : %zu MiB\n",
sdram_size_mb());
printk(BIOS_INFO, "MB: SPIclk : %llu kHz\n",
spi_get_clock(0) >> 10);
}
extern const struct bdk_devicetree_key_value devtree[];
static void mainboard_init(struct device *dev)
{
size_t i;
/* Init UARTs */
for (i = 0; i < 4; i++) {
if (!uart_is_enabled(i))
uart_setup(i, 0);
}
/* Init timer */
soc_timer_init();
/* Init CPUs */
for (i = 1; i < CONFIG_MAX_CPUS; i++)
start_cpu(i, NULL);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = &mainboard_init;
bdk_config_set_fdt(devtree);
mainboard_print_info();
}
struct chip_operations mainboard_ops = {
.name = CONFIG_MAINBOARD_PART_NUMBER,
.enable_dev = mainboard_enable,
};

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/*
* This file is part of the coreboot project.
*
* Copyright 2017-present Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define ELGON_GPIO_ERROR_LED 11
#define ELGON_GPIO_SPI_MUX 24
#define ELGON_GPIO_UART_SEL 26

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#include <soc/memlayout.ld>

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/*
* This file is part of the coreboot project.
*
* Copyright 2017-present Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <arch/exception.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#include <soc/sdram.h>
#include <soc/timer.h>
#include <soc/mmu.h>
#include <stdlib.h>
#include <console/console.h>
#include <program_loading.h>
#include <libbdk-hal/bdk-config.h>
#include <string.h>
#include <arch/stages.h>
extern const struct bdk_devicetree_key_value devtree[];
void platform_romstage_main(void)
{
watchdog_poke(0);
console_init();
exception_init();
bdk_config_set_fdt(devtree);
sdram_init();
soc_mmu_init();
watchdog_poke(0);
cbmem_initialize_empty();
run_ramstage();
}

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FLASH@0x0 16M {
# must use a power of two in MiB for WP_RO
WP_RO@0x0 0x400000 {
RO_SECTION@0x0 0x3fc000 {
# 0 - 0x10000 is free for firmware usage.
# bootblock starts at 0x20000
FMAP@0x0 0x1000
RO_FRID@0x1000 0x100
# bootblock includes trusted/non-trusted CLIB, CSIB,
# and BL1FWs packaged in
# src/soc/cavium/common/Makefile.inc.
BOOTBLOCK@0x10000 0x70000
COREBOOT(CBFS)@0x80000 0x2fc000
GBB@0x37c000 0x80000
}
RO_VPD@0x3fc000 0x4000
}
RW_SECTION_A@0x400000 0x5fa000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x5f7f00
RW_FWID_A@0x5f9f00 0x100
}
RW_SECTION_B@0x9fa000 0x5fa000 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x5f7f00
RW_FWID_B@0x5f9f00 0x100
}
RW_ELOG@0xff4000 0x4000
RW_VPD@0xff8000 0x8000
}