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soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage 

PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.

TEST=Build and boot sarien/arcada.

Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Subrata Banik 2019-09-11 10:32:31 +05:30 committed by Patrick Georgi
parent d589c8681e
commit 8cced29eed
7 changed files with 0 additions and 9 deletions
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1
src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
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@ -32,7 +32,6 @@ chip soc/intel/cannonlake
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"

1
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/cannonlake
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"

1
src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
View File

@ -34,7 +34,6 @@ chip soc/intel/cannonlake
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"

1
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/cannonlake
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"

1
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -34,7 +34,6 @@ chip soc/intel/cannonlake
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"

3
src/soc/intel/cannonlake/chip.h
View File

@ -387,9 +387,6 @@ struct soc_intel_cannonlake_config {
uint8_t SlowSlewRateForSa;
uint8_t SlowSlewRateForFivr;
/* DMI Power Optimizer */
uint8_t dmipwroptimize;
/* SATA Power Optimizer */
uint8_t satapwroptimize;

1
src/soc/intel/cannonlake/fsp_params.c
View File

@ -377,7 +377,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
/* Power Optimizer */
params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
/* Disable PCH ACPI timer */