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mainboard/google/reef: Configure PERST_0 pin 

This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.

BUG=chrome-os-partner:55877

Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Vaibhav Shankar 2016-09-14 10:39:29 -07:00 committed by Aaron Durbin
parent ef8deaffcb
commit 8cdeef1c0d
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/reef/variants/baseboard/devicetree.cb
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@ -12,6 +12,10 @@ chip soc/intel/apollolake
register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_PRT0_UDEF"
# EMMC TX DATA Delay 1 # EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3. # Refer to EDS-Vol2-22.3.