mb/google/endeavour: chrontel: fix interrupt and compat string
The devicetree declares the chrontel interrupt as GpioInt so the GPIO needs to be configured as such instead of routing directly to APIC. Also update the compatible string to conform to kernel standards. BUG=b:146576073 TEST=install ch7322 driver; send commands using cec-ctl and verify that the interrupt handler is called. Change-Id: I737d951db135c53deb0f3cb956f0d0f275082251 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -27,9 +27,9 @@ static const struct pad_config gpio_table[] = {
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/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */
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/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ISH_GP0 */ PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
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/* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */
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/* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
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/* ISH_GP2 */ PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP), /* 7322_INTO */
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/* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */
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/* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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@ -137,7 +137,7 @@ chip soc/intel/skylake
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "desc" = ""Chrontel 7322""
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register "uid" = "1"
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register "compat_string" = ""chrontel,7322""
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register "compat_string" = ""chrontel,ch7322""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)"
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device i2c 75 on end
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end
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@ -145,7 +145,7 @@ chip soc/intel/skylake
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "desc" = ""Chrontel 7322""
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register "uid" = "2"
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register "compat_string" = ""chrontel,7322""
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register "compat_string" = ""chrontel,ch7322""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
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device i2c 76 on end
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end
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