include/console: Rename and update POST_ENTRY_RAMSTAGE postcode

Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f
to make the ramstage postcodes appear in an incremental order.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/include/console/post_codes.h

@@ -111,6 +111,14 @@
  */
 #define POST_PRE_HARDWAREMAIN			0x6e
 
+/**
+ * \brief Entry into coreboot in RAM stage main()
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has successfully loaded and started executing.
+ */
+#define POST_ENTRY_HARDWAREMAIN			0x6f
+
 /**
  * \brief Before Device Probe
  *
@@ -195,14 +203,6 @@
  */
 #define POST_BS_PAYLOAD_BOOT			0x7b
 
-/**
- * \brief Entry into coreboot in RAM stage main()
- *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has successfully loaded and started executing.
- */
-#define POST_ENTRY_RAMSTAGE                     0x80
-
 /**
  * \brief Before calling FSP Notify before End of Firmware
  *

src/lib/hardwaremain.c

@@ -442,7 +442,7 @@ void main(void)
 	cbmem_initialize();
 
 	timestamp_add_now(TS_START_RAMSTAGE);
-	post_code(POST_ENTRY_RAMSTAGE);
+	post_code(POST_ENTRY_HARDWAREMAIN);
 
 	/* Handoff sleep type from romstage. */
 	acpi_is_wakeup_s3();