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mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RST 

BUG=b:133000685

Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Aamir Bohra 2019-09-10 08:51:02 +05:30 committed by Furquan Shaikh
parent 87bb5f5e7a
commit 8dda419b3c
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -24,6 +24,8 @@ chip soc/intel/cannonlake
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
# Configure devslp pad reset to PLT_RST
register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset"
register "satapwroptimize" = "1"
# Enable System Agent dynamic frequency
register "SaGv" = "SaGv_Enabled"