start of epia-m port
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
550999eaca
commit
8e0586200b
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@ -0,0 +1,241 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_STREAM
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=5
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object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -O -mcpu=c3 ./auto.E "
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## Setup our mtrrs
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##
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# mainboardinit cpu/p6/earlymtrr.inc
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit ./auto.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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northbridge via/vt8601 "vt8601"
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# pci 0:0.0
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# pci 0:1.0
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southbridge via/vt8231 "vt8231"
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# pci 0:11.0
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# pci 0:11.1
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# pci 0:11.2
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# pci 0:11.3
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# pci 0:11.4
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# pci 0:11.5
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# pci 0:11.6
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# pci 0:12.0
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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register "enable_com_ports" = "1"
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register "enable_keyboard" = "0"
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register "enable_nvram" = "1"
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end
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end
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cpu p6 "cpu0"
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end
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##
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## Include the old serial code for those few places that still need it.
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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@ -0,0 +1,140 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8601/raminit.h"
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#include "cpu/p6/earlymtrr.c"
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/*
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*/
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void udelay(int usecs)
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{
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "debug.c"
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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static void memreset_setup(void)
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{
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}
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/*
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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}
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#include "northbridge/via/vt8601/raminit.c"
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/*
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#include "sdram/generic_sdram.c"
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*/
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static void enable_mainboard_devices(void)
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{
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device_t dev;
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/* dev 0 for southbridge */
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dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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#if 0
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// This early setup switches IDE into compatibility mode before PCI gets
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// // a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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//
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#endif
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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*/
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dev += 0x100; /* ICKY */
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pci_write_config8(dev, 0x42, 0);
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}
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static void enable_shadow_ram(void)
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{
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static void main(void)
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{
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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uart_init();
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console_init();
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enable_mainboard_devices();
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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sdram_set_spd_registers((const struct mem_controller *) 0);
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sdram_enable(0, (const struct mem_controller *) 0);
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/* Check all of memory */
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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early_mtrr_init();
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}
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struct chip_control mainboard_via_epia_control;
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struct mainboard_via_epia_config {
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int nothing;
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};
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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||||
}
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#if 0
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
|
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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||||
print_debug("bad device\r\n");
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||||
break;
|
||||
}
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||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
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print_debug_char(' ');
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}
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||||
print_debug("\r\n");
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||||
}
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||||
device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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||||
print_debug_hex8(i);
|
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print_debug(".1: ");
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print_debug_hex8(device);
|
||||
for(j = 0; j < 256; j++) {
|
||||
int status;
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||||
unsigned char byte;
|
||||
if ((j & 0xf) == 0) {
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(j);
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||||
print_debug(": ");
|
||||
}
|
||||
status = smbus_read_byte(device, j);
|
||||
if (status < 0) {
|
||||
print_debug("bad device\r\n");
|
||||
break;
|
||||
}
|
||||
byte = status & 0xff;
|
||||
print_debug_hex8(byte);
|
||||
print_debug_char(' ');
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
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||||
#endif
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@ -0,0 +1,29 @@
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|||
#define ASSEMBLY 1
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||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "cpu/p6/boot_cpu.c"
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
/* for now, just always assume failure */
|
||||
|
||||
#if 0
|
||||
/* Is this a cpu reset? */
|
||||
if (cpu_init_detected()) {
|
||||
if (last_boot_normal()) {
|
||||
asm("jmp __normal_image");
|
||||
} else {
|
||||
asm("jmp __cpu_reset");
|
||||
}
|
||||
}
|
||||
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
asm("jmp __normal_image");
|
||||
}
|
||||
#endif
|
||||
}
|
|
@ -0,0 +1,32 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*5, /* there can be total 5 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0x88, /* Where the interrupt router lies (dev) */
|
||||
0x1c20, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x8231, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* 8231 ethernet */
|
||||
{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
|
||||
/* 8231 internal */
|
||||
{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
|
||||
/* PCI slot */
|
||||
{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
|
||||
{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
|
||||
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
|
||||
}
|
||||
};
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/chip.h>
|
||||
#include "chip.h"
|
||||
|
||||
static int
|
||||
mainboard_scan_bus(device_t root, int maxbus)
|
||||
{
|
||||
int retval;
|
||||
printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
|
||||
retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
|
||||
printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
|
||||
return maxbus;
|
||||
}
|
||||
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = mainboard_scan_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for(child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_via_epia_control = {
|
||||
.enumerate = enumerate,
|
||||
.name = "VIA EPIA mainboard ",
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#if 0
|
||||
//#include "arch/romcc_io.h"
|
||||
#include <arch/io.h>
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x7) << 8))
|
||||
|
||||
static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outb(value, 0xCFC + (addr & 3));
|
||||
}
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outl(value, 0xCFC);
|
||||
}
|
||||
|
||||
static unsigned pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
return inl(0xCFC);
|
||||
}
|
||||
|
||||
#include "../../../northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,2 @@
|
|||
config chip.h
|
||||
object northbridge.o
|
|
@ -0,0 +1,5 @@
|
|||
struct northbridge_via_vt8601_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_control northbridge_via_vt8601_control;
|
|
@ -0,0 +1,122 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <mem.h>
|
||||
#include <part/sizeram.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <device/chip.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <bitops.h>
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
|
||||
struct mem_range *sizeram(void)
|
||||
{
|
||||
unsigned long mmio_basek;
|
||||
static struct mem_range mem[10];
|
||||
device_t dev;
|
||||
int i, idx;
|
||||
unsigned char rambits;
|
||||
|
||||
dev = dev_find_slot(0, 0);
|
||||
if (!dev) {
|
||||
printk_err("Cannot find PCI: 0:0\n");
|
||||
return 0;
|
||||
}
|
||||
mem[0].basek = 0;
|
||||
mem[0].sizek = 65536;
|
||||
idx = 1;
|
||||
while(idx < sizeof(mem)/sizeof(mem[0])) {
|
||||
mem[idx].basek = 0;
|
||||
mem[idx].sizek = 0;
|
||||
idx++;
|
||||
}
|
||||
for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
|
||||
unsigned char reg;
|
||||
reg = pci_read_config8(dev, ramregs[i]);
|
||||
/* these are ENDING addresses, not sizes.
|
||||
* if there is memory in this slot, then reg will be > rambits.
|
||||
* So we just take the max, that gives us total.
|
||||
* We take the highest one to cover for once and future linuxbios
|
||||
* bugs. We warn about bugs.
|
||||
*/
|
||||
if (reg > rambits)
|
||||
rambits = reg;
|
||||
if (reg < rambits)
|
||||
printk_err("ERROR! register 0x%x is not set!\n",
|
||||
ramregs[i]);
|
||||
}
|
||||
|
||||
printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
|
||||
mem[0].sizek = rambits*8*1024;
|
||||
#if 1
|
||||
for(i = 0; i < idx; i++) {
|
||||
printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
|
||||
i, mem[i].basek, i, mem[i].sizek);
|
||||
}
|
||||
#endif
|
||||
|
||||
return mem;
|
||||
}
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
extern struct device_operations default_pci_ops_bus;
|
||||
chip_enumerate(chip);
|
||||
chip->dev->ops = &default_pci_ops_bus;
|
||||
}
|
||||
|
||||
/*
|
||||
* This fixup is based on capturing values from an Award bios. Without
|
||||
* this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
|
||||
* slower than normal, ethernet drops packets).
|
||||
* Apparently these registers govern some sort of bus master behavior.
|
||||
*/
|
||||
static void random_fixup() {
|
||||
device_t pcidev = dev_find_slot(0, 0);
|
||||
|
||||
printk_spew("VT8601 random fixup ...\n");
|
||||
if (pcidev) {
|
||||
pci_write_config8(pcidev, 0x70, 0xc0);
|
||||
pci_write_config8(pcidev, 0x71, 0x88);
|
||||
pci_write_config8(pcidev, 0x72, 0xec);
|
||||
pci_write_config8(pcidev, 0x73, 0x0c);
|
||||
pci_write_config8(pcidev, 0x74, 0x0e);
|
||||
pci_write_config8(pcidev, 0x75, 0x81);
|
||||
pci_write_config8(pcidev, 0x76, 0x52);
|
||||
}
|
||||
}
|
||||
|
||||
static void northbridge_init(struct chip *chip, enum chip_pass pass)
|
||||
{
|
||||
|
||||
struct northbridge_via_vt8601_config *conf =
|
||||
(struct northbridge_via_vt8601_config *)chip->chip_info;
|
||||
|
||||
switch (pass) {
|
||||
case CONF_PASS_PRE_PCI:
|
||||
break;
|
||||
|
||||
case CONF_PASS_POST_PCI:
|
||||
break;
|
||||
|
||||
case CONF_PASS_PRE_BOOT:
|
||||
random_fixup();
|
||||
break;
|
||||
|
||||
default:
|
||||
/* nothing yet */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_control northbridge_via_vt8601_control = {
|
||||
.enumerate = enumerate,
|
||||
.enable = northbridge_init,
|
||||
.name = "VIA vt8601 Northbridge",
|
||||
};
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef NORTHBRIDGE_VIA_VT8601_H
|
||||
#define NORTHBRIDGE_VIA_VT8601_H
|
||||
|
||||
extern unsigned int vt8601_scan_root_bus(device_t root, unsigned int max);
|
||||
|
||||
#endif /* NORTHBRIDGE_VIA_VT8601_H */
|
|
@ -0,0 +1,394 @@
|
|||
#include <cpu/p6/mtrr.h>
|
||||
#include "raminit.h"
|
||||
|
||||
/*
|
||||
This software and ancillary information (herein called SOFTWARE )
|
||||
called LinuxBIOS is made available under the terms described
|
||||
here. The SOFTWARE has been approved for release with associated
|
||||
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
|
||||
been authored by an employee or employees of the University of
|
||||
California, operator of the Los Alamos National Laboratory under
|
||||
Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
|
||||
U.S. Government has rights to use, reproduce, and distribute this
|
||||
SOFTWARE. The public may copy, distribute, prepare derivative works
|
||||
and publicly display this SOFTWARE without charge, provided that this
|
||||
Notice and any statement of authorship are reproduced on all copies.
|
||||
Neither the Government nor the University makes any warranty, express
|
||||
or implied, or assumes any liability or responsibility for the use of
|
||||
this SOFTWARE. If SOFTWARE is modified to produce derivative works,
|
||||
such modified SOFTWARE should be clearly marked, so as not to confuse
|
||||
it with the version available from LANL.
|
||||
*/
|
||||
/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
|
||||
* rminnich@lanl.gov
|
||||
*/
|
||||
/*
|
||||
* 11/26/02 - kevinh@ispiri.com - The existing comments implied that
|
||||
* this didn't work yet. Therefore, I've updated it so that it works
|
||||
* correctly - at least on my VIA epia motherboard. 64MB DIMM in slot 0.
|
||||
*/
|
||||
|
||||
/* Added automatic detection of first equipped bank and its MA mapping type.
|
||||
* (Rest of configuration is done in C)
|
||||
* 5/19/03 by SONE Takeshi <ts1@tsn.or.jp>
|
||||
*/
|
||||
/* converted to C 9/2003 Ron Minnich */
|
||||
|
||||
/* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB
|
||||
* frequency is 133MHz. If your CPU runs at another bus speed, you
|
||||
* might need to change some of register values.
|
||||
*/
|
||||
#ifndef DIMM_PC133
|
||||
#define DIMM_PC133 0
|
||||
#endif
|
||||
|
||||
// Set to 1 if your DIMMs are CL=2
|
||||
#ifndef DIMM_CL2
|
||||
#define DIMM_CL2 0
|
||||
#endif
|
||||
|
||||
void dimms_read(unsigned long x)
|
||||
{
|
||||
uint8_t c;
|
||||
unsigned long eax;
|
||||
volatile unsigned long y;
|
||||
eax = x;
|
||||
for(c = 0; c < 6; c++) {
|
||||
y = * (volatile unsigned long *) eax;
|
||||
eax += 0x10000000;
|
||||
}
|
||||
}
|
||||
|
||||
void dimms_write(int x)
|
||||
{
|
||||
uint8_t c;
|
||||
unsigned long eax = x;
|
||||
for(c = 0; c < 6; c++) {
|
||||
*(volatile unsigned long *) eax = 0;
|
||||
eax += 0x10000000;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#ifdef DEBUG_SETNORTHB
|
||||
void setnorthb(device_t north, uint8_t reg, uint8_t val)
|
||||
{
|
||||
print_debug("setnorth: reg ");
|
||||
print_debug_hex8(reg);
|
||||
print_debug(" to ");
|
||||
print_debug_hex8(val);
|
||||
print_debug("\r\n");
|
||||
pci_write_config8(north, reg, val);
|
||||
}
|
||||
#else
|
||||
#define setnorthb pci_write_config8
|
||||
#endif
|
||||
|
||||
void
|
||||
dumpnorth(device_t north)
|
||||
{
|
||||
uint8_t r, c;
|
||||
for(r = 0; r < 256; r += 16) {
|
||||
print_debug_hex8(r);
|
||||
print_debug(":");
|
||||
for(c = 0; c < 16; c++) {
|
||||
print_debug_hex8(pci_read_config8(north, r+c));
|
||||
print_debug(" ");
|
||||
}
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void sdram_set_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
device_t north = (device_t) 0;
|
||||
uint8_t c, r;
|
||||
|
||||
print_err("vt8601 init starting\r\n");
|
||||
north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
|
||||
north = 0;
|
||||
print_debug_hex32(north);
|
||||
print_debug(" is the north\n");
|
||||
print_debug_hex16(pci_read_config16(north, 0));
|
||||
print_debug(" ");
|
||||
print_debug_hex16(pci_read_config16(north, 2));
|
||||
print_debug("\r\n");
|
||||
|
||||
/* All we are doing now is setting initial known-good values that will
|
||||
* be revised later as we read SPD
|
||||
*/
|
||||
// memory clk enable. We are not using ECC
|
||||
pci_write_config8(north,0x78, 0x01);
|
||||
print_debug_hex8(pci_read_config8(north, 0x78));
|
||||
// dram control, see the book.
|
||||
#if DIMM_PC133
|
||||
pci_write_config8(north,0x68, 0x52);
|
||||
#else
|
||||
pci_write_config8(north,0x68, 0x42);
|
||||
#endif
|
||||
// dram control, see the book.
|
||||
pci_write_config8(north,0x6B, 0x0c);
|
||||
// Initial setting, 256MB in each bank, will be rewritten later.
|
||||
pci_write_config8(north,0x5A, 0x20);
|
||||
print_debug_hex8(pci_read_config8(north, 0x5a));
|
||||
pci_write_config8(north,0x5B, 0x40);
|
||||
pci_write_config8(north,0x5C, 0x60);
|
||||
pci_write_config8(north,0x5D, 0x80);
|
||||
pci_write_config8(north,0x5E, 0xA0);
|
||||
pci_write_config8(north,0x5F, 0xC0);
|
||||
// It seems we have to take care of these 2 registers as if
|
||||
// they are bank 6 and 7.
|
||||
pci_write_config8(north,0x56, 0xC0);
|
||||
pci_write_config8(north,0x57, 0xC0);
|
||||
|
||||
// SDRAM in all banks
|
||||
pci_write_config8(north,0x60, 0x3F);
|
||||
// DRAM timing. I'm suspicious of this
|
||||
// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
|
||||
// ras precharge 4T, RAS pulse 5T
|
||||
// cas2 is 0xd6, cas3 is 0xe6
|
||||
// we're also backing off write pulse width to 2T, so result is 0xee
|
||||
#if DIMM_CL2
|
||||
pci_write_config8(north,0x64, 0xd4);
|
||||
pci_write_config8(north,0x65, 0xd4);
|
||||
pci_write_config8(north,0x66, 0xd4);
|
||||
#else // CL=3
|
||||
pci_write_config8(north,0x64, 0xe4);
|
||||
pci_write_config8(north,0x65, 0xe4);
|
||||
pci_write_config8(north,0x66, 0xe4);
|
||||
#endif
|
||||
|
||||
// dram frequency select.
|
||||
// enable 4K pages for 64M dram.
|
||||
#if DIMM_PC133
|
||||
pci_write_config8(north,0x69, 0x3c);
|
||||
#else
|
||||
pci_write_config8(north,0x69, 0xac);
|
||||
#endif
|
||||
|
||||
/* IMPORTANT -- disable refresh counter */
|
||||
// refresh counter, disabled.
|
||||
pci_write_config8(north,0x6A, 0x00);
|
||||
|
||||
|
||||
// clkenable configuration. kevinh FIXME - add precharge
|
||||
pci_write_config8(north,0x6C, 0x00);
|
||||
// dram read latch delay of 1 ns, MD drive 8 mA,
|
||||
// high drive strength on MA[2: 13], we#, cas#, ras#
|
||||
// As per Cindy Lee, set to 0x37, not 0x57
|
||||
pci_write_config8(north,0x6D, 0x7f);
|
||||
}
|
||||
|
||||
/* slot is the dram slot. Return size of side0 in lower 16-bit,
|
||||
* side1 in upper 16-bit, in units of 8MB */
|
||||
static unsigned long
|
||||
spd_module_size(unsigned char slot)
|
||||
{
|
||||
/* for all the DRAMS, see if they are there and get the size of each
|
||||
* module. This is just a very early first cut at sizing.
|
||||
*/
|
||||
/* we may run out of registers ... */
|
||||
unsigned int banks, rows, cols, reg;
|
||||
unsigned int value = 0;
|
||||
unsigned int module = ((0x50 + slot) << 1) + 1;
|
||||
/* is the module there? if byte 2 is not 4, then we'll assume it
|
||||
* is useless.
|
||||
*/
|
||||
print_info("Slot ");
|
||||
print_info_hex8(slot);
|
||||
if (smbus_read_byte(module, 2) != 4) {
|
||||
print_info(" is empty\r\n");
|
||||
return 0;
|
||||
}
|
||||
print_info(" is SDRAM ");
|
||||
|
||||
banks = smbus_read_byte(module, 17);
|
||||
/* we're going to assume symmetric banks. Sorry. */
|
||||
cols = smbus_read_byte(module, 4) & 0xf;
|
||||
rows = smbus_read_byte(module, 3) & 0xf;
|
||||
/* grand total. You have rows+cols addressing, * times of banks, times
|
||||
* width of data in bytes */
|
||||
/* Width is assumed to be 64 bits == 8 bytes */
|
||||
value = (1 << (cols + rows)) * banks * 8;
|
||||
print_info_hex32(value);
|
||||
print_info(" bytes ");
|
||||
/* Return in 8MB units */
|
||||
value >>= 23;
|
||||
|
||||
/* We should have single or double side */
|
||||
if (smbus_read_byte(module, 5) == 2) {
|
||||
print_info("x2");
|
||||
value = (value << 16) | value;
|
||||
}
|
||||
print_info("\r\n");
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static int
|
||||
spd_num_chips(unsigned char slot)
|
||||
{
|
||||
unsigned int module = ((0x50 + slot) << 1) + 1;
|
||||
unsigned int width;
|
||||
|
||||
width = smbus_read_byte(module, 13);
|
||||
if (width == 0)
|
||||
width = 8;
|
||||
return 64 / width;
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
#define T133 7
|
||||
unsigned char Trp = 1, Tras = 1, casl = 2, val;
|
||||
unsigned char timing = 0xe4;
|
||||
/* read Trp */
|
||||
val = smbus_read_byte(0xa0, 27);
|
||||
if (val < 2*T133)
|
||||
Trp = 1;
|
||||
val = smbus_read_byte(0xa0, 30);
|
||||
if (val < 5*T133)
|
||||
Tras = 0;
|
||||
val = smbus_read_byte(0xa0, 18);
|
||||
if (val < 8)
|
||||
casl = 1;
|
||||
if (val < 4)
|
||||
casl = 0;
|
||||
|
||||
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
|
||||
|
||||
print_debug_hex8(val); print_debug(" is the computed timing\n");
|
||||
/* don't set it. Experience shows that this screwy chipset should just
|
||||
* be run with the most conservative timing.
|
||||
* pci_write_config8(0, 0x64, val);
|
||||
*/
|
||||
}
|
||||
|
||||
static void set_ma_mapping(device_t north, int slot, int type)
|
||||
{
|
||||
unsigned char reg, val;
|
||||
int shift;
|
||||
|
||||
reg = 0x58 + slot/2;
|
||||
if (slot%2 >= 1)
|
||||
shift = 0;
|
||||
else
|
||||
shift = 4;
|
||||
|
||||
val = pci_read_config8(north, reg);
|
||||
val &= ~(0xf << shift);
|
||||
val |= type << shift;
|
||||
pci_write_config8(north, reg, val);
|
||||
}
|
||||
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
unsigned char i;
|
||||
static const uint8_t ramregs[] = {
|
||||
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
|
||||
};
|
||||
device_t north = 0;
|
||||
uint32_t size, base, slot, ma;
|
||||
/* begin to initialize*/
|
||||
// I forget why we need this, but we do
|
||||
dimms_write(0xa55a5aa5);
|
||||
|
||||
/* set NOP*/
|
||||
pci_write_config8(north,0x6C, 0x01);
|
||||
print_debug("NOP\r\n");
|
||||
/* wait 200us*/
|
||||
// You need to do the memory reference. That causes the nop cycle.
|
||||
dimms_read(0);
|
||||
udelay(400);
|
||||
print_debug("PRECHARGE\r\n");
|
||||
/* set precharge */
|
||||
pci_write_config8(north,0x6C, 0x02);
|
||||
print_debug("DUMMY READS\r\n");
|
||||
/* dummy reads*/
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_debug("CBR\r\n");
|
||||
/* set CBR*/
|
||||
pci_write_config8(north,0x6C, 0x04);
|
||||
|
||||
/* do 8 reads and wait >100us between each - from via*/
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_debug("MRS\r\n");
|
||||
/* set MRS*/
|
||||
pci_write_config8(north,0x6c, 0x03);
|
||||
#if DIMM_CL2
|
||||
dimms_read(0x150);
|
||||
#else // CL=3
|
||||
dimms_read(0x1d0);
|
||||
#endif
|
||||
udelay(200);
|
||||
print_debug("NORMAL\r\n");
|
||||
/* set to normal mode */
|
||||
pci_write_config8(north,0x6C, 0x08);
|
||||
|
||||
dimms_write(0x55aa55aa);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_debug("set ref. rate\r\n");
|
||||
// Set the refresh rate.
|
||||
#if DIMM_PC133
|
||||
pci_write_config8(north,0x6A, 0x86);
|
||||
#else
|
||||
pci_write_config8(north,0x6A, 0x65);
|
||||
#endif
|
||||
print_debug("enable multi-page open\r\n");
|
||||
// enable multi-page open
|
||||
pci_write_config8(north,0x6B, 0x0d);
|
||||
|
||||
base = 0;
|
||||
for(slot = 0; slot < 4; slot++) {
|
||||
size = spd_module_size(slot);
|
||||
/* side 0 */
|
||||
base += size & 0xffff;
|
||||
pci_write_config8(north, ramregs[2*slot], base);
|
||||
/* side 1 */
|
||||
base += size >> 16;
|
||||
if (base > 0xff)
|
||||
base = 0xff;
|
||||
pci_write_config8(north, ramregs[2*slot + 1], base);
|
||||
|
||||
if (!size)
|
||||
continue;
|
||||
|
||||
/* Calculate the value of MA mapping type register,
|
||||
* based on size of SDRAM chips. */
|
||||
size = (size & 0xffff) << (3 + 3);
|
||||
/* convert module size to be in Mbits */
|
||||
size /= spd_num_chips(slot);
|
||||
print_debug_hex16(size);
|
||||
print_debug(" is the chip size\r\n");
|
||||
if (size < 64)
|
||||
ma = 0;
|
||||
if (size < 256)
|
||||
ma = 8;
|
||||
else
|
||||
ma = 0xe;
|
||||
print_debug_hex16(ma);
|
||||
print_debug(" is the MA type\r\n");
|
||||
set_ma_mapping(north, slot, ma);
|
||||
}
|
||||
print_err("vt8601 done\r\n");
|
||||
dumpnorth(north);
|
||||
}
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
struct mem_controller {
|
||||
int empty;
|
||||
};
|
||||
|
||||
#endif /* RAMINIT_H */
|
|
@ -0,0 +1,2 @@
|
|||
config chip.h
|
||||
object vt8231.o
|
|
@ -0,0 +1,21 @@
|
|||
#ifndef _SOUTHBRIDGE_VIA_VT8231
|
||||
#define _SOUTHBRIDGE_VIA_VT8231
|
||||
|
||||
extern struct chip_control southbridge_via_vt8231_control;
|
||||
|
||||
struct southbridge_via_vt8231_config {
|
||||
/* PCI function enables */
|
||||
/* i.e. so that pci scan bus will find them. */
|
||||
/* I am putting in IDE as an example but obviously this needs
|
||||
* to be more complete!
|
||||
*/
|
||||
int enable_ide;
|
||||
/* enables of functions of devices */
|
||||
int enable_usb;
|
||||
int enable_native_ide;
|
||||
int enable_com_ports;
|
||||
int enable_keyboard;
|
||||
int enable_nvram;
|
||||
};
|
||||
|
||||
#endif /* _SOUTHBRIDGE_VIA_VT8231 */
|
|
@ -0,0 +1,106 @@
|
|||
# Sample config file for EPIA
|
||||
# This will make a target directory of ./epia.512kflash
|
||||
|
||||
loadoptions
|
||||
|
||||
target epia.512kflash
|
||||
|
||||
uses ARCH
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CPU_FIXUP
|
||||
uses FALLBACK_SIZE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses HAVE_HARD_RESET
|
||||
uses i586
|
||||
uses i686
|
||||
uses INTEL_PPRO_MTRR
|
||||
uses HEAP_SIZE
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses MEMORY_HOLE
|
||||
uses PAYLOAD_SIZE
|
||||
uses _RAMBASE
|
||||
uses _ROMBASE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SIZE
|
||||
uses STACK_SIZE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_OPTION_TABLE
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses MAINBOARD
|
||||
uses CONFIG_CHIP_CONFIGURE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
|
||||
option CONFIG_CHIP_CONFIGURE=1
|
||||
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
option CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
option CPU_FIXUP=1
|
||||
option CONFIG_UDELAY_TSC=0
|
||||
option i686=1
|
||||
option i586=1
|
||||
option INTEL_PPRO_MTRR=1
|
||||
|
||||
option ROM_SIZE=524288
|
||||
|
||||
|
||||
option HAVE_OPTION_TABLE=1
|
||||
option CONFIG_ROM_STREAM=1
|
||||
option HAVE_FALLBACK_BOOT=1
|
||||
|
||||
###
|
||||
### Compute the location and size of where this firmware image
|
||||
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||
###
|
||||
option FALLBACK_SIZE=131072
|
||||
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
option _RAMBASE=0x00004000
|
||||
|
||||
#
|
||||
###
|
||||
### Compute the start location and size size of
|
||||
### The linuxBIOS bootloader.
|
||||
###
|
||||
|
||||
#
|
||||
# Arima hdama
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
mainboard via/epia
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
payload ../../../../../lnxieepro100.ebi
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
mainboard via/epia
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
payload ../../../../../lnxieepro100.ebi
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
|
@ -0,0 +1,106 @@
|
|||
# Sample config file for EPIA
|
||||
# This will make a target directory of ./epia
|
||||
|
||||
loadoptions
|
||||
|
||||
target epia
|
||||
|
||||
uses ARCH
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CPU_FIXUP
|
||||
uses FALLBACK_SIZE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses HAVE_HARD_RESET
|
||||
uses i586
|
||||
uses i686
|
||||
uses INTEL_PPRO_MTRR
|
||||
uses HEAP_SIZE
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses MEMORY_HOLE
|
||||
uses PAYLOAD_SIZE
|
||||
uses _RAMBASE
|
||||
uses _ROMBASE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SIZE
|
||||
uses STACK_SIZE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_OPTION_TABLE
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses MAINBOARD
|
||||
uses CONFIG_CHIP_CONFIGURE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
|
||||
option CONFIG_CHIP_CONFIGURE=1
|
||||
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
option CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
option CPU_FIXUP=1
|
||||
option CONFIG_UDELAY_TSC=0
|
||||
option i686=1
|
||||
option i586=1
|
||||
option INTEL_PPRO_MTRR=1
|
||||
option ROM_SIZE=256*1024
|
||||
|
||||
option HAVE_OPTION_TABLE=1
|
||||
option CONFIG_ROM_STREAM=1
|
||||
option HAVE_FALLBACK_BOOT=1
|
||||
|
||||
###
|
||||
### Compute the location and size of where this firmware image
|
||||
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||
###
|
||||
option FALLBACK_SIZE=131072
|
||||
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
option _RAMBASE=0x00004000
|
||||
|
||||
#
|
||||
###
|
||||
### Compute the start location and size size of
|
||||
### The linuxBIOS bootloader.
|
||||
###
|
||||
|
||||
#
|
||||
# Arima hdama
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
mainboard via/epia
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
payload ../../../../../../filo.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
mainboard via/epia
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
payload ../../../../../../filo.elf
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
|
@ -0,0 +1,107 @@
|
|||
# Sample config file for EPIA
|
||||
# This will make a target directory of ./epia
|
||||
|
||||
loadoptions
|
||||
|
||||
target epia
|
||||
|
||||
uses ARCH
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CPU_FIXUP
|
||||
uses FALLBACK_SIZE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses HAVE_HARD_RESET
|
||||
uses i586
|
||||
uses i686
|
||||
uses INTEL_PPRO_MTRR
|
||||
uses HEAP_SIZE
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses MEMORY_HOLE
|
||||
uses PAYLOAD_SIZE
|
||||
uses _RAMBASE
|
||||
uses _ROMBASE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SIZE
|
||||
uses STACK_SIZE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses USE_OPTION_TABLE
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses MAINBOARD
|
||||
uses CONFIG_CHIP_CONFIGURE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses TTYS0_BAUD
|
||||
|
||||
option TTYS0_BAUD=19200
|
||||
|
||||
option CONFIG_CHIP_CONFIGURE=1
|
||||
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=7
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
option CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
option CPU_FIXUP=1
|
||||
option CONFIG_UDELAY_TSC=0
|
||||
option i686=1
|
||||
option i586=1
|
||||
option INTEL_PPRO_MTRR=1
|
||||
option ROM_SIZE=256*1024
|
||||
|
||||
option HAVE_OPTION_TABLE=1
|
||||
option CONFIG_ROM_STREAM=1
|
||||
option HAVE_FALLBACK_BOOT=1
|
||||
|
||||
###
|
||||
### Compute the location and size of where this firmware image
|
||||
### (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||
###
|
||||
option FALLBACK_SIZE=131072
|
||||
|
||||
## LinuxBIOS C code runs at this location in RAM
|
||||
option _RAMBASE=0x00004000
|
||||
|
||||
#
|
||||
###
|
||||
### Compute the start location and size size of
|
||||
### The linuxBIOS bootloader.
|
||||
###
|
||||
|
||||
#
|
||||
# Arima hdama
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
mainboard via/epia
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
payload ../../../../../lnxieepro100.ebi
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
mainboard via/epia
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
payload ../../../../../lnxieepro100.ebi
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
Loading…
Reference in New Issue