t132: Add timestamp collection support in t132

Add a region TIMESTAMP to store all the timestamps starting from bootblock to
end of romstage. At the end of romstage take all the timestamps in TIMESTAMP
region and put it into cbmem

BUG=chrome-os-partner:32973
BRANCH=None
TEST=Compiles successfully and cbmem -t prints all timestamps

Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223110
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>

(cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1
Reviewed-on: http://review.coreboot.org/10736
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh 2014-10-13 14:50:08 -07:00 committed by Patrick Georgi
parent ac630f7070
commit 8e584aed2a
5 changed files with 13 additions and 0 deletions

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@ -15,6 +15,7 @@ config SOC_NVIDIA_TEGRA132
select SMP select SMP
select ARM64_USE_SECURE_MONITOR select ARM64_USE_SECURE_MONITOR
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAS_PRECBMEM_TIMESTAMP_REGION
if SOC_NVIDIA_TEGRA132 if SOC_NVIDIA_TEGRA132

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@ -26,6 +26,7 @@
#include <soc/clock.h> #include <soc/clock.h>
#include <soc/nvidia/tegra/apbmisc.h> #include <soc/nvidia/tegra/apbmisc.h>
#include <soc/power.h> #include <soc/power.h>
#include <timestamp.h>
#define BCT_OFFSET_IN_BIT 0x50 #define BCT_OFFSET_IN_BIT 0x50
#define ODMDATA_OFFSET_IN_BCT 0x6A8 #define ODMDATA_OFFSET_IN_BCT 0x6A8
@ -57,6 +58,9 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void)
void main(void) void main(void)
{ {
timestamp_init(0);
timestamp_add_now(TS_START_BOOTBLOCK);
// enable JTAG at the earliest stage // enable JTAG at the earliest stage
enable_jtag(); enable_jtag();

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@ -36,6 +36,7 @@ SECTIONS
PRERAM_CBFS_CACHE(0x40002000, 72K) PRERAM_CBFS_CACHE(0x40002000, 72K)
VBOOT2_WORK(0x40014000, 16K) VBOOT2_WORK(0x40014000, 16K)
STACK(0x40018000, 2K) STACK(0x40018000, 2K)
TIMESTAMP(0x40018800, 2K)
BOOTBLOCK(0x40019000, 22K) BOOTBLOCK(0x40019000, 22K)
VERSTAGE(0x4001e800, 58K) VERSTAGE(0x4001e800, 58K)
ROMSTAGE(0x4002d000, 76K) ROMSTAGE(0x4002d000, 76K)

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@ -31,6 +31,7 @@
#include <soc/sdram_configs.h> #include <soc/sdram_configs.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <timer.h> #include <timer.h>
#include <timestamp.h>
void __attribute__((weak)) romstage_mainboard_init(void) void __attribute__((weak)) romstage_mainboard_init(void)
{ {
@ -39,6 +40,8 @@ void __attribute__((weak)) romstage_mainboard_init(void)
void romstage(void) void romstage(void)
{ {
timestamp_add_now(TS_START_ROMSTAGE);
console_init(); console_init();
exception_init(); exception_init();
@ -52,6 +55,8 @@ void romstage(void)
printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
#endif #endif
timestamp_add_now(TS_AFTER_INITRAM);
/* /*
* Trust Zone needs to be initialized after the DRAM initialization * Trust Zone needs to be initialized after the DRAM initialization
* because carveout registers are programmed during DRAM init. * because carveout registers are programmed during DRAM init.

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@ -24,6 +24,7 @@
#include <console/console.h> #include <console/console.h>
#include <soc/verstage.h> #include <soc/verstage.h>
#include <program_loading.h> #include <program_loading.h>
#include <timestamp.h>
void __attribute__((weak)) verstage_mainboard_init(void) void __attribute__((weak)) verstage_mainboard_init(void)
{ {
@ -33,6 +34,7 @@ void __attribute__((weak)) verstage_mainboard_init(void)
static void verstage(void) static void verstage(void)
{ {
console_init(); console_init();
timestamp_add_now(TS_START_VBOOT);
exception_init(); exception_init();
verstage_mainboard_init(); verstage_mainboard_init();