mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented code
Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16967 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
a8802577ea
commit
8e64174137
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@ -140,7 +140,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
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};
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LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
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LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
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/* Enable IMC fan control. the recommended way */
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#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
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@ -158,8 +158,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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/* Thermal Zone Parameter */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; //6 | BIT3;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; /* BIT0 | BIT2 | BIT5 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00; /* 6 | BIT3 */
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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@ -170,15 +170,15 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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/* IMC Fan Policy temperature thresholds */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0; /* AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /* AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /* AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
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/* IMC Fan Policy PWM Settings */
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@ -195,7 +195,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; /* BIT0 | BIT2 | BIT5 */
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
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@ -205,20 +205,20 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /* AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /* AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /* AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /* AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /* AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /* AC5 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /* AC6 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /* AC7 lowest threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /* critical threshold* in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /* Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
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@ -230,7 +230,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
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@ -241,7 +241,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; /* BIT0 | BIT2 | BIT5 */
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
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@ -251,7 +251,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
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/* IMC Function */
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FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; //BIT0 | BIT4 |BIT8;
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FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333; /*BIT0 | BIT4 |BIT8; */
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/* NOTE:
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* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
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@ -279,7 +279,6 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
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FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
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FchParams->FchReset.SataEnable = hudson_sata_enable();
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FchParams->FchReset.IdeEnable = hudson_ide_enable();
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@ -118,66 +118,66 @@ OemCustomizeInitEarly (
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* use its default conservative settings.
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*/
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static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
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//
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// The following macros are supported (use comma to separate macros):
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//
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// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
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// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
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// AGESA will base on this value to disable unused MemClk to save power.
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// Example:
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// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
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// Bit AM3/S1g3 pin name
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// 0 M[B,A]_CLK_H/L[0]
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// 1 M[B,A]_CLK_H/L[1]
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// 2 M[B,A]_CLK_H/L[2]
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// 3 M[B,A]_CLK_H/L[3]
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// 4 M[B,A]_CLK_H/L[4]
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// 5 M[B,A]_CLK_H/L[5]
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// 6 M[B,A]_CLK_H/L[6]
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// 7 M[B,A]_CLK_H/L[7]
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// And platform has the following routing:
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// CS0 M[B,A]_CLK_H/L[4]
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// CS1 M[B,A]_CLK_H/L[2]
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// CS2 M[B,A]_CLK_H/L[3]
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// CS3 M[B,A]_CLK_H/L[5]
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// Then platform can specify the following macro:
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// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
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//
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// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
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// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
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// AGESA will base on this value to tristate unused CKE to save power.
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//
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// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
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// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
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// AGESA will base on this value to tristate unused ODT pins to save power.
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//
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// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
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// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
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// AGESA will base on this value to tristate unused Chip select to save power.
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//
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// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
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// Specifies the number of DIMM slots per channel.
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//
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// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
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// Specifies the number of Chip selects per channel.
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//
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// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
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// Specifies the number of channels per socket.
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//
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// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
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// Specifies DDR bus speed of channel ChannelID on socket SocketID.
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//
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// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
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// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
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//
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// WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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// Byte6Seed, Byte7Seed, ByteEccSeed)
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// Specifies the write leveling seed for a channel of a socket.
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//
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// HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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// Byte6Seed, Byte7Seed, ByteEccSeed)
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// Speicifes the HW RXEN training seed for a channel of a socket
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//
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/*
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* The following macros are supported (use comma to separate macros):
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*
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* MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
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* The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
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* AGESA will base on this value to disable unused MemClk to save power.
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* Example:
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* BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
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* Bit AM3/S1g3 pin name
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* 0 M[B,A]_CLK_H/L[0]
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* 1 M[B,A]_CLK_H/L[1]
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* 2 M[B,A]_CLK_H/L[2]
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* 3 M[B,A]_CLK_H/L[3]
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* 4 M[B,A]_CLK_H/L[4]
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* 5 M[B,A]_CLK_H/L[5]
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* 6 M[B,A]_CLK_H/L[6]
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* 7 M[B,A]_CLK_H/L[7]
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* And platform has the following routing:
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* CS0 M[B,A]_CLK_H/L[4]
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* CS1 M[B,A]_CLK_H/L[2]
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* CS2 M[B,A]_CLK_H/L[3]
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* CS3 M[B,A]_CLK_H/L[5]
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* Then platform can specify the following macro:
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* MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
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*
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* CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
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* The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
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* AGESA will base on this value to tristate unused CKE to save power.
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*
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* ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
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* The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
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* AGESA will base on this value to tristate unused ODT pins to save power.
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*
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* CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
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* The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
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* AGESA will base on this value to tristate unused Chip select to save power.
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*
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* NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
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* Specifies the number of DIMM slots per channel.
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*
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* NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
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* Specifies the number of Chip selects per channel.
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*
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* NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
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* Specifies the number of channels per socket.
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*
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* OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
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* Specifies DDR bus speed of channel ChannelID on socket SocketID.
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*
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* DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
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* Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
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*
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* WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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* Byte6Seed, Byte7Seed, ByteEccSeed)
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* Specifies the write leveling seed for a channel of a socket.
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*
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* HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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* Byte6Seed, Byte7Seed, ByteEccSeed)
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* Speicifes the HW RXEN training seed for a channel of a socket
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*/
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#define SEED_WL 0x0E
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WRITE_LEVELING_SEED(
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@ -81,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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AGESAWRAPPER(amdinitpost);
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//PspMboxBiosCmdDramInfo();
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post_code(0x41);
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AGESAWRAPPER(amdinitenv);
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/*
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