soc/amd/cezanne,common: factor out CPPC code to common AMD SoC code

The Cezanne CPPC ACPI table generation code also applies to Sabrina, so
move it to the common AMD SoC code directory so that it can be used for
Sabrina too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/Kconfig

@@ -39,6 +39,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_ALIB
+	select SOC_AMD_COMMON_BLOCK_ACPI_CPPC
 	select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
 	select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
 	select SOC_AMD_COMMON_BLOCK_AOAC

src/soc/amd/cezanne/Makefile.inc

@@ -31,7 +31,6 @@ romstage-y	+= uart.c
 ramstage-y	+= acpi.c
 ramstage-y	+= agesa_acpi.c
 ramstage-y	+= chip.c
-ramstage-y	+= cppc.c
 ramstage-y	+= cpu.c
 ramstage-y	+= data_fabric.c
 ramstage-y	+= fch.c

src/soc/amd/cezanne/acpi.c

@@ -5,6 +5,7 @@
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
 #include <amdblocks/acpi.h>
+#include <amdblocks/cppc.h>
 #include <amdblocks/cpu.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/ioapic.h>
@@ -19,7 +20,6 @@
 #include <soc/msr.h>
 #include <types.h>
 #include "chip.h"
-#include <soc/cppc.h>
 
 unsigned long acpi_fill_madt(unsigned long current)
 {

src/soc/amd/common/block/acpi/Kconfig

@@ -8,6 +8,9 @@ config SOC_AMD_COMMON_BLOCK_ACPI
 config SOC_AMD_COMMON_BLOCK_ACPI_ALIB
 	bool
 
+config SOC_AMD_COMMON_BLOCK_ACPI_CPPC
+	bool
+
 config SOC_AMD_COMMON_BLOCK_ACPI_GPIO
 	bool
 

src/soc/amd/common/block/acpi/Makefile.inc

@@ -11,6 +11,7 @@ ramstage-y += pm_state.c
 ramstage-y += tables.c
 ramstage-$(CONFIG_ACPI_BERT) += bert.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC) += cppc.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS) += ivrs.c
 

src/soc/amd/common/block/acpi/cppc.c

@@ -2,8 +2,8 @@
 
 #include <acpi/acpi_pm.h>
 #include <acpi/acpigen.h>
+#include <amdblocks/cppc.h>
 #include <arch/cpu.h>
-#include <soc/cppc.h>
 #include <soc/msr.h>
 
 /*