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soc/intel/common: Update comment on HFSTS1.spi_protection_mode 

The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.

For information on EOM status, please refer secton# 3.6.1 in doc#
612229.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sridhar Siricilla 2022-09-12 10:37:17 +05:30 committed by Felix Held
parent 6580674b34
commit 90a439384b
1 changed files with 7 additions and 5 deletions
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12
src/soc/intel/common/block/cse/cse.c
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@ -271,12 +271,14 @@ bool cse_is_hfs1_com_soft_temp_disable(void)
} }
/* /*
* TGL HFSTS1.spi_protection_mode bit replaces the previous * Starting from TGL platform, HFSTS1.spi_protection_mode replaces mfg_mode to indicate
* `manufacturing mode (mfg_mode)` without changing the offset and purpose * SPI protection status as well as end-of-manufacturing(EOM) status where EOM flow is
* of this bit. * triggered in single staged operation (either through first boot with required MFIT
* configuratin or FPT /CLOSEMANUF).
* In staged manufacturing flow, spi_protection_mode alone doesn't indicate the EOM status.
* *
* Using HFSTS1.mfg_mode to get the SPI protection status for all PCH. * HFSTS1.spi_protection_mode description:
* mfg_mode = 0 means SPI protection in on. * mfg_mode = 0 means SPI protection is on.
* mfg_mode = 1 means SPI is unprotected. * mfg_mode = 1 means SPI is unprotected.
*/ */
bool cse_is_hfs1_spi_protected(void) bool cse_is_hfs1_spi_protected(void)