soc/intel/broadwell: Implement postcar stage
This does the following: - Reuse the cpu/intel/car/non-evict CAR setup and exit. - Use postcar_frame functions to set up the postcar frame Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
9fca297ca4
commit
90cca5422d
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@ -40,6 +40,8 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SPI_CONSOLE_SUPPORT
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select CPU_INTEL_COMMON
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select INTEL_GMA_ACPI
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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config PCIEXP_ASPM
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bool
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@ -30,6 +30,7 @@ ramstage-y += me_status.c
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romstage-y += me_status.c
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ramstage-y += memmap.c
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romstage-y += memmap.c
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postcar-y += memmap.c
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ramstage-y += minihd.c
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ramstage-y += monotonic_timer.c
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smm-y += monotonic_timer.c
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@ -55,6 +56,7 @@ ramstage-y += spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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ramstage-y += stage_cache.c
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romstage-y += stage_cache.c
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postcar-y += stage_cache.c
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ramstage-y += systemagent.c
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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@ -65,6 +67,8 @@ ramstage-y += ehci.c
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ramstage-y += xhci.c
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smm-y += xhci.c
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postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S
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ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
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cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
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@ -19,7 +19,7 @@
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
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#if defined(__SIMPLE_DEVICE__)
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#include <arch/io.h>
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#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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@ -1,4 +1,4 @@
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cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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romstage-y += cpu.c
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romstage-y += pch.c
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@ -8,6 +8,5 @@ romstage-y += report_platform.c
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romstage-y += romstage.c
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romstage-y += smbus.c
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romstage-y += spi.c
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romstage-y += stack.c
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romstage-y += systemagent.c
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romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
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@ -1,318 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
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* and the space used by the reference code. These 2 values combined should
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* be a power of 2 because the MTRR setup assumes that. */
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#define CACHE_AS_RAM_SIZE \
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(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
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/* Cache 4GB - MRC_SIZE_KB for MRC */
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#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
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#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
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#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
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#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS
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#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
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#define NoEvictMod_MSR 0x2e0
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/* Save the BIST result. */
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movl %eax, %ebp
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* All CPUs need to be in Wait for SIPI state */
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wait_for_sipi:
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movl (%esi), %eax
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bt $12, %eax
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jc wait_for_sipi
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post_code(0x21)
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) >> 1), %edi
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xorl %eax, %eax
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xorl %edx, %edx
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clear_mtrrs:
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movw (%esi), %bx
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movzx %bx, %ecx
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wrmsr
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add $2, %esi
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dec %edi
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jnz clear_mtrrs
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post_code(0x22)
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/* Configure the default memory type to uncacheable. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(0x23)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x24)
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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post_code(0x25)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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invd
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movl %eax, %cr0
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/* enable the 'no eviction' mode */
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movl $NoEvictMod_MSR, %ecx
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rdmsr
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orl $1, %eax
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andl $~2, %eax
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wrmsr
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/* Clear the cache memory region. This will also fill up the cache */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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/* enable the 'no eviction run' state */
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movl $NoEvictMod_MSR, %ecx
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rdmsr
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orl $3, %eax
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wrmsr
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post_code(0x26)
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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movl $CPU_PHYSMASK_HI, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x27)
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/* Enable caching for RAM init code to run faster */
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movl $MTRR_PHYS_BASE(2), %ecx
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movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRR_PHYS_MASK(2), %ecx
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movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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post_code(0x28)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CACHE_AS_RAM_LIMIT), %eax
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movl %eax, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* Build the call frame. */
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movl %esp, %ebp
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movd %mm1, %ebx
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pushl %ebx
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movd %mm0, %ebx
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pushl %ebx
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pushl %eax
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before_romstage:
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post_code(0x29)
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/* Call romstage.c main function. */
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call romstage_main
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/* Save return value from romstage_main. It contains the stack to use
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* after cache-as-ram is torn down. It also contains the information
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* for setting up MTRRs. */
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movl %eax, %ebx
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post_code(0x2f)
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post_code(0x30)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~MTRR_DEF_TYPE_EN), %eax
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wrmsr
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post_code(0x31)
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/* Disable the no eviction run state */
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movl $NoEvictMod_MSR, %ecx
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rdmsr
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andl $~2, %eax
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wrmsr
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invd
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/* Disable the no eviction mode */
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rdmsr
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andl $~1, %eax
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wrmsr
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/* Clear MTRR that was used to cache MRC */
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xorl %eax, %eax
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xorl %edx, %edx
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movl $MTRR_PHYS_BASE(2), %ecx
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wrmsr
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movl $MTRR_PHYS_MASK(2), %ecx
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wrmsr
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post_code(0x33)
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/* Enable cache. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x36)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Setup stack as indicated by return value from romstage_main(). */
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movl %ebx, %esp
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/* Get number of MTRRs. */
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popl %ebx
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movl $MTRR_PHYS_BASE(0), %ecx
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1:
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testl %ebx, %ebx
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jz 1f
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/* Low 32 bits of MTRR base. */
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popl %eax
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/* Upper 32 bits of MTRR base. */
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popl %edx
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/* Write MTRR base. */
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wrmsr
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inc %ecx
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/* Low 32 bits of MTRR mask. */
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popl %eax
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/* Upper 32 bits of MTRR mask. */
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popl %edx
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/* Write MTRR mask. */
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wrmsr
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inc %ecx
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dec %ebx
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jmp 1b
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1:
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post_code(0x39)
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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post_code(0x3b)
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/* Invalidate the cache again. */
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invd
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post_code(0x3c)
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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call romstage_after_car
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.Lhlt:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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mtrr_table:
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/* Fixed MTRRs */
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.word 0x250, 0x258, 0x259
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.word 0x268, 0x269, 0x26A
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.word 0x26B, 0x26C, 0x26D
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.word 0x26E, 0x26F
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/* Variable MTRRs */
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.word 0x200, 0x201, 0x202, 0x203
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.word 0x204, 0x205, 0x206, 0x207
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.word 0x208, 0x209, 0x20A, 0x20B
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.word 0x20C, 0x20D, 0x20E, 0x20F
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.word 0x210, 0x211, 0x212, 0x213
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mtrr_table_end:
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@ -19,6 +19,7 @@
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#include <arch/cbfs.h>
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#include <arch/early_variables.h>
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#include <bootmode.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <elog.h>
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@ -32,6 +33,36 @@
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#include <soc/romstage.h>
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#include <soc/spi.h>
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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static void platform_enter_postcar(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
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MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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}
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/* Entry from cache-as-ram.inc. */
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asmlinkage void *romstage_main(unsigned long bist,
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uint32_t tsc_low, uint32_t tsc_hi)
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@ -74,7 +105,9 @@ asmlinkage void *romstage_main(unsigned long bist,
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/* Call into mainboard. */
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mainboard_romstage_entry(&rp);
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return setup_stack_and_mtrrs();
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platform_enter_postcar();
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return NULL;
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}
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/* Entry from the mainboard. */
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@ -1,104 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <cbmem.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <program_loading.h>
|
||||
|
||||
static inline uint32_t *stack_push(u32 *stack, u32 value)
|
||||
{
|
||||
stack = &stack[-1];
|
||||
*stack = value;
|
||||
return stack;
|
||||
}
|
||||
|
||||
/* setup_stack_and_mtrrs() determines the stack to use after
|
||||
* cache-as-ram is torn down as well as the MTRR settings to use. */
|
||||
void *setup_stack_and_mtrrs(void)
|
||||
{
|
||||
int num_mtrrs;
|
||||
uint32_t *slot;
|
||||
uint32_t mtrr_mask_upper;
|
||||
uint32_t top_of_ram;
|
||||
|
||||
/* Top of stack needs to be aligned to a 4-byte boundary. */
|
||||
slot = (void *)romstage_ram_stack_top();
|
||||
num_mtrrs = 0;
|
||||
|
||||
/* The upper bits of the MTRR mask need to set according to the number
|
||||
* of physical address bits. */
|
||||
mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
|
||||
|
||||
/* The order for each MTRR is value then base with upper 32-bits of
|
||||
* each value coming before the lower 32-bits. The reasoning for
|
||||
* this ordering is to create a stack layout like the following:
|
||||
* +0: Number of MTRRs
|
||||
* +4: MTRR base 0 31:0
|
||||
* +8: MTRR base 0 63:32
|
||||
* +12: MTRR mask 0 31:0
|
||||
* +16: MTRR mask 0 63:32
|
||||
* +20: MTRR base 1 31:0
|
||||
* +24: MTRR base 1 63:32
|
||||
* +28: MTRR mask 1 31:0
|
||||
* +32: MTRR mask 1 63:32
|
||||
*/
|
||||
|
||||
/* Cache the ROM as WP just below 4GiB. */
|
||||
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
|
||||
slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
|
||||
slot = stack_push(slot, 0); /* upper base */
|
||||
slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
|
||||
num_mtrrs++;
|
||||
|
||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
|
||||
slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
|
||||
slot = stack_push(slot, 0); /* upper base */
|
||||
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
|
||||
num_mtrrs++;
|
||||
|
||||
top_of_ram = (uint32_t)cbmem_top();
|
||||
/* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
|
||||
* start of the TSEG region. It is required to be 8MiB aligned. Set
|
||||
* this area as cacheable so it can be used later for ramstage before
|
||||
* setting up the entire RAM as cacheable. */
|
||||
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
|
||||
slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
|
||||
slot = stack_push(slot, 0); /* upper base */
|
||||
slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
|
||||
num_mtrrs++;
|
||||
|
||||
/* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
|
||||
* region resides. However, it is not restricted to SMM mode until
|
||||
* SMM has been relocated. By setting the region to cacheable it
|
||||
* provides faster access when relocating the SMM handler as well
|
||||
* as using the TSEG region for other purposes. */
|
||||
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
|
||||
slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
|
||||
slot = stack_push(slot, 0); /* upper base */
|
||||
slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
|
||||
num_mtrrs++;
|
||||
|
||||
/* Save the number of MTRRs to setup. Return the stack location
|
||||
* pointing to the number of MTRRs. */
|
||||
slot = stack_push(slot, num_mtrrs);
|
||||
|
||||
return slot;
|
||||
}
|
||||
Loading…
Reference in New Issue