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mb/google/rex: Update DQS for Rex 

Update the DQS for Rex as per the latest Rex schematics (08/25).

BUG=b:243734885
TEST=Built successfully. Confirmed on HW.

Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Tarun Tuli 2022-08-24 23:47:14 -04:00 committed by Subrata Banik
parent a35c0e81b6
commit 90eca85596
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/rex/variants/baseboard/rex/memory.c
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@ -50,14 +50,14 @@ static const struct mb_cfg baseboard_memcfg = {
/* DQS CPU<>DRAM map */ /* DQS CPU<>DRAM map */
.lpx_dqs_map = { .lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 }, .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 }, .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr2 = { .dqs0 = 1, .dqs1 = 0 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 1, .dqs1 = 0 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 }, .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 }, .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }, .ddr7 = { .dqs0 = 1, .dqs1 = 0 },
}, },
.lp5x_config = { .lp5x_config = {