mb/google/dedede/var/driblee: Configure thermal sensor setting
According to schematics, TSR2 thermal sensor is not present in driblee. BUG=b:191732473, b:197180925, b:195868075 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -41,6 +41,42 @@ chip soc/intel/jasperlake
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register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
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device domain 0 on
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device pci 04.0 on
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chip drivers/intel/dptf
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)
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}"
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## Power Limits Control
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 20000,
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.max_power = 20000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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device generic 0 on end
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end
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end # SA Thermal device
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device pci 14.0 on
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chip drivers/usb/acpi
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device usb 0.0 on
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