mb/google/brya: Implement SLP_S0_GATE signal

The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to
provide an indication to the rest of the platform when the system is
entering its software-initiated low-power state (i.e. S0ix). This lets
the platform distinguish between opportunistic S0ix entry and the runtime
suspend mechanism.

BUG=b:180401723
TEST=abuild

Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-02-18 09:40:15 -07:00
parent 0c7aef73ac
commit 914ea8e530
3 changed files with 32 additions and 4 deletions

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@ -22,6 +22,8 @@ DefinitionBlock(
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {
#include "mainboard.asl"
Device (PCI0) Device (PCI0)
{ {
#include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/common/block/acpi/acpi/northbridge.asl>

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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/*
* On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of
* the platform can transition to its low power state as well.
*/
\_SB.PCI0.CTXS(GPIO_SLP_S0_GATE);
} Else {
/*
* On S0ix exit, set the SLP_S0_GATE pin, so that the rest of
* the platform will resume from its low power state.
*/
\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
}
}

View File

@ -14,5 +14,7 @@
#define GPIO_PCH_WP GPP_E15 #define GPIO_PCH_WP GPP_E15
/* EC in RW or RO */ /* EC in RW or RO */
#define GPIO_EC_IN_RW GPP_F18 #define GPIO_EC_IN_RW GPP_F18
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_F9
#endif /* __BASEBOARD_GPIO_H__ */ #endif /* __BASEBOARD_GPIO_H__ */