soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom
Use the common acpi_fill_root_complex_tom function instead of the SoC- level northbridge_fill_ssdt_generator function that does basically the same. TEST=Resulting coreboot SSDT remains unchanged on Careena. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/biosram.h>
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#include <amdblocks/hda.h>
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#include <device/pci_ops.h>
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@ -186,27 +187,6 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
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return (unsigned long)current;
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}
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static void northbridge_fill_ssdt_generator(const struct device *device)
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{
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msr_t msr;
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char pscope[] = "\\_SB.PCI0";
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acpigen_write_scope(pscope);
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msr = rdmsr(TOP_MEM);
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acpigen_write_name_dword("TOM1", msr.lo);
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msr = rdmsr(TOP_MEM2);
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/*
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* Since XP only implements parts of ACPI 2.0, we can't use a qword
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* here.
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* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
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* slide 22ff.
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* Shift value right by 20 bit to make it fit into 32bit,
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* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
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*/
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acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
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acpigen_pop_len();
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}
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static unsigned long agesa_write_acpi_tables(const struct device *device,
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unsigned long current,
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acpi_rsdp_t *rsdp)
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@ -285,7 +265,7 @@ struct device_operations stoneyridge_northbridge_operations = {
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.set_resources = set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.acpi_fill_ssdt = northbridge_fill_ssdt_generator,
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.acpi_fill_ssdt = acpi_fill_root_complex_tom,
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.write_acpi_tables = agesa_write_acpi_tables,
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};
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