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amd/stoneyridge: Add SPI controller driver 

Add more definitions for the controller registers and fields.  Add
source that is adapted from hudson and updated for Stoney Ridge.

This was tested with follow-on patches that write S3 data to flash.

BUG=b:68992021

Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Marshall Dawson 2017-11-08 22:18:38 -07:00 committed by Martin Roth
parent 6d941bad78
commit 918c8717b2
3 changed files with 234 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/stoneyridge/Makefile.inc
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@ -91,12 +91,14 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
ramstage-y += usb.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
smm-y += smihandler.c
smm-y += smi_util.c
smm-y += sb_util.c
smm-y += tsc_freq.c
smm-$(CONFIG_DEBUG_SMI) += uart.c
smm-$(CONFIG_SPI_FLASH) += spi.c
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include

26
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -197,7 +197,11 @@
#define LPC_HOST_CONTROL 0xbb
#define SPI_FROM_HOST_PREFETCH_EN BIT(0)
/* SPI Controller */
#define SPI_FIFO_DEPTH 8
#define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31)
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
/* Nominal is 16.7MHz on older devices, 33MHz on newer */
#define SPI_READ_MODE_NOM 0x00000000
@ -207,14 +211,34 @@
#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))
#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )
#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))
#define SPI_FIFO_PTR_CLR BIT(20)
#define SPI_ARB_ENABLE BIT(19)
#define EXEC_OPCODE BIT(16)
#define SPI_REG_CNTRL01 0x01
#define SPI_REG_CNTRL02 0x02
#define SPI_FIFO_PTR_CLR02 (SPI_FIFO_PTR_CLR >> 16)
#define SPI_CNTRL1 0x0c
#define SPI_FIFO_PTR_MASK (BIT(8) | BIT(9) | BIT(10))
#define SPI_CNTRL11 0x0d
#define SPI_FIFO_PTR_MASK11 (SPI_FIFO_PTR_MASK >> 8)
#define SPI100_SPEED_CONFIG 0x22
/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
#define SPI_NORM_SPEED_SH 12
#define SPI_FAST_SPEED_SH 8
#define SPI_EXT_INDEX 0x1e
#define SPI_EXT_DATA 0x1f
#define SPI_DDR_CMD 0x0
#define SPI_QDR_CMD 0x1
#define SPI_DPR_CMD 0x2
#define SPI_QPR_CMD 0x3
#define SPI_MODE_BYTE 0x4
#define SPI_TX_BYTE_COUNT 0x5
#define SPI_RX_BYTE_COUNT 0x6
#define SPI_SPI_DATA_FIFO_PTR 0x7
#define SPI100_ENABLE 0x20
#define SPI_USE_SPI100 BIT(0)

207
src/soc/amd/stoneyridge/spi.c Normal file
View File

@ -0,0 +1,207 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>
#include <arch/early_variables.h>
#include <timer.h>
#include <console/console.h>
#include <commonlib/helpers.h>
#include <spi_flash.h>
#include <spi-generic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <soc/imc.h>
static uintptr_t spibar CAR_GLOBAL;
static uintptr_t get_spibase(void)
{
return *(uintptr_t *)car_get_var_ptr(&spibar);
}
static void set_spibar(uintptr_t base)
{
*(uintptr_t *)car_get_var_ptr(&spibar) = base;
}
static inline uint8_t spi_read8(uint8_t reg)
{
return read8((void *)(get_spibase() + reg));
}
static inline uint32_t spi_read32(uint8_t reg)
{
return read32((void *)(get_spibase() + reg));
}
static inline void spi_write8(uint8_t reg, uint8_t val)
{
write8((void *)(get_spibase() + reg), val);
}
static inline void spi_write32(uint8_t reg, uint32_t val)
{
write32((void *)(get_spibase() + reg), val);
}
static int reset_internal_fifo_pointer(void)
{
uint8_t reg;
const uint32_t timeout_ms = 500;
struct stopwatch sw;
stopwatch_init_msecs_expire(&sw, timeout_ms);
do {
reg = spi_read8(SPI_REG_CNTRL02);
reg |= SPI_FIFO_PTR_CLR02;
spi_write8(SPI_REG_CNTRL02, reg);
/* wait for ptr=0 */
if (!(spi_read8(SPI_CNTRL11) & (SPI_FIFO_PTR_MASK11)))
return 0;
} while (!stopwatch_expired(&sw));
printk(BIOS_DEBUG, "FCH SPI Error: FIFO reset failed\n");
return -1;
}
static int execute_command(void)
{
uint32_t reg;
const uint32_t timeout_ms = 500;
struct stopwatch sw;
stopwatch_init_msecs_expire(&sw, timeout_ms);
reg = spi_read32(SPI_CNTRL0);
reg |= EXEC_OPCODE;
spi_write32(SPI_CNTRL0, reg);
do {
if (!(spi_read32(SPI_CNTRL0) & (EXEC_OPCODE | SPI_BUSY)))
return 0;
} while (!stopwatch_expired(&sw));
printk(BIOS_DEBUG, "FCH SPI Error: Timeout executing command\n");
return -1;
}
void spi_init(void)
{
uintptr_t bar;
bar = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
bar = ALIGN_DOWN(bar, 64);
set_spibar(bar);
}
static int do_command(uint8_t cmd, const void *dout,
size_t bytesout, void *din, size_t *bytesin)
{
size_t count;
size_t max_in = MIN(*bytesin, SPI_FIFO_DEPTH);
spi_write8(SPI_EXT_INDEX, SPI_TX_BYTE_COUNT);
spi_write8(SPI_EXT_DATA, bytesout);
spi_write8(SPI_EXT_INDEX, SPI_RX_BYTE_COUNT);
spi_write8(SPI_EXT_DATA, max_in);
spi_write8(SPI_CNTRL0, cmd);
if (reset_internal_fifo_pointer())
return -1;
for (count = 0; count < bytesout; count++, dout++)
spi_write8(SPI_CNTRL1, *(uint8_t *)dout);
if (execute_command())
return -1;
if (reset_internal_fifo_pointer())
return -1;
for (count = 0; count < bytesout; count++)
spi_read8(SPI_CNTRL1); /* skip the bytes we sent */
for (count = 0; count < max_in; count++, din++)
*(uint8_t *)din = spi_read8(SPI_CNTRL1);
*bytesin -= max_in;
return 0;
}
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
size_t bytesout, void *din, size_t bytesin)
{
uint8_t cmd;
/* First byte is cmd which cannot be sent through FIFO */
cmd = *(uint8_t *)dout++;
bytesout--;
/*
* Check if this is a write command attempting to transfer more bytes
* than the controller can handle. Iterations for writes are not
* supported here because each SPI write command needs to be preceded
* and followed by other SPI commands, and this sequence is controlled
* by the SPI chip driver.
*/
if (bytesout > SPI_FIFO_DEPTH) {
printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI"
" chip driver use spi_crop_chunk()?\n");
return -1;
}
do {
if (do_command(cmd, dout, bytesout, din, &bytesin))
return -1;
} while (bytesin);
return 0;
}
int chipset_volatile_group_begin(const struct spi_flash *flash)
{
if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
imc_sleep();
return 0;
}
int chipset_volatile_group_end(const struct spi_flash *flash)
{
if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
imc_wakeup();
return 0;
}
static const struct spi_ctrlr spi_ctrlr = {
.xfer = spi_ctrlr_xfer,
.xfer_vector = spi_xfer_two_vectors,
.max_xfer_size = SPI_FIFO_DEPTH,
.deduct_cmd_len = true,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{
.ctrlr = &spi_ctrlr,
.bus_start = 0,
.bus_end = 0,
},
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);