amd/stoneyridge: Add SPI controller driver
Add more definitions for the controller registers and fields. Add source that is adapted from hudson and updated for Stoney Ridge. This was tested with follow-on patches that write S3 data to flash. BUG=b:68992021 Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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@ -91,12 +91,14 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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ramstage-y += usb.c
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ramstage-y += usb.c
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ramstage-y += tsc_freq.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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smm-y += smihandler.c
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smm-y += smihandler.c
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smm-y += smi_util.c
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smm-y += smi_util.c
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smm-y += sb_util.c
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smm-y += sb_util.c
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smm-y += tsc_freq.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_DEBUG_SMI) += uart.c
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smm-$(CONFIG_DEBUG_SMI) += uart.c
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smm-$(CONFIG_SPI_FLASH) += spi.c
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
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CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
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@ -197,7 +197,11 @@
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#define LPC_HOST_CONTROL 0xbb
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#define LPC_HOST_CONTROL 0xbb
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#define SPI_FROM_HOST_PREFETCH_EN BIT(0)
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#define SPI_FROM_HOST_PREFETCH_EN BIT(0)
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/* SPI Controller */
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#define SPI_FIFO_DEPTH 8
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#define SPI_CNTRL0 0x00
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#define SPI_CNTRL0 0x00
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#define SPI_BUSY BIT(31)
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#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
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#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
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/* Nominal is 16.7MHz on older devices, 33MHz on newer */
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/* Nominal is 16.7MHz on older devices, 33MHz on newer */
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#define SPI_READ_MODE_NOM 0x00000000
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#define SPI_READ_MODE_NOM 0x00000000
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@ -207,14 +211,34 @@
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#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))
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#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))
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#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )
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#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )
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#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))
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#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))
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#define SPI_FIFO_PTR_CLR BIT(20)
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#define SPI_ARB_ENABLE BIT(19)
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#define SPI_ARB_ENABLE BIT(19)
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#define EXEC_OPCODE BIT(16)
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#define SPI_REG_CNTRL01 0x01
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#define SPI_REG_CNTRL02 0x02
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#define SPI_FIFO_PTR_CLR02 (SPI_FIFO_PTR_CLR >> 16)
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#define SPI_CNTRL1 0x0c
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#define SPI_CNTRL1 0x0c
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#define SPI_FIFO_PTR_MASK (BIT(8) | BIT(9) | BIT(10))
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#define SPI_CNTRL11 0x0d
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#define SPI_FIFO_PTR_MASK11 (SPI_FIFO_PTR_MASK >> 8)
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#define SPI100_SPEED_CONFIG 0x22
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/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
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/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
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#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
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#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
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#define SPI_NORM_SPEED_SH 12
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#define SPI_NORM_SPEED_SH 12
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#define SPI_FAST_SPEED_SH 8
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#define SPI_FAST_SPEED_SH 8
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#define SPI_EXT_INDEX 0x1e
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#define SPI_EXT_DATA 0x1f
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#define SPI_DDR_CMD 0x0
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#define SPI_QDR_CMD 0x1
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#define SPI_DPR_CMD 0x2
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#define SPI_QPR_CMD 0x3
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#define SPI_MODE_BYTE 0x4
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#define SPI_TX_BYTE_COUNT 0x5
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#define SPI_RX_BYTE_COUNT 0x6
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#define SPI_SPI_DATA_FIFO_PTR 0x7
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#define SPI100_ENABLE 0x20
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#define SPI100_ENABLE 0x20
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#define SPI_USE_SPI100 BIT(0)
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#define SPI_USE_SPI100 BIT(0)
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@ -0,0 +1,207 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <arch/io.h>
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#include <arch/early_variables.h>
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#include <timer.h>
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <spi_flash.h>
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#include <spi-generic.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <soc/southbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/imc.h>
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static uintptr_t spibar CAR_GLOBAL;
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static uintptr_t get_spibase(void)
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{
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return *(uintptr_t *)car_get_var_ptr(&spibar);
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}
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static void set_spibar(uintptr_t base)
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{
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*(uintptr_t *)car_get_var_ptr(&spibar) = base;
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}
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static inline uint8_t spi_read8(uint8_t reg)
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{
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return read8((void *)(get_spibase() + reg));
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}
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static inline uint32_t spi_read32(uint8_t reg)
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{
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return read32((void *)(get_spibase() + reg));
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}
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static inline void spi_write8(uint8_t reg, uint8_t val)
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{
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write8((void *)(get_spibase() + reg), val);
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}
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static inline void spi_write32(uint8_t reg, uint32_t val)
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{
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write32((void *)(get_spibase() + reg), val);
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}
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static int reset_internal_fifo_pointer(void)
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{
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uint8_t reg;
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const uint32_t timeout_ms = 500;
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, timeout_ms);
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do {
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reg = spi_read8(SPI_REG_CNTRL02);
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reg |= SPI_FIFO_PTR_CLR02;
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spi_write8(SPI_REG_CNTRL02, reg);
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/* wait for ptr=0 */
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if (!(spi_read8(SPI_CNTRL11) & (SPI_FIFO_PTR_MASK11)))
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return 0;
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} while (!stopwatch_expired(&sw));
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printk(BIOS_DEBUG, "FCH SPI Error: FIFO reset failed\n");
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return -1;
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}
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static int execute_command(void)
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{
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uint32_t reg;
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const uint32_t timeout_ms = 500;
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, timeout_ms);
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reg = spi_read32(SPI_CNTRL0);
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reg |= EXEC_OPCODE;
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spi_write32(SPI_CNTRL0, reg);
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do {
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if (!(spi_read32(SPI_CNTRL0) & (EXEC_OPCODE | SPI_BUSY)))
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return 0;
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} while (!stopwatch_expired(&sw));
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printk(BIOS_DEBUG, "FCH SPI Error: Timeout executing command\n");
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return -1;
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}
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void spi_init(void)
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{
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uintptr_t bar;
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bar = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
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bar = ALIGN_DOWN(bar, 64);
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set_spibar(bar);
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}
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static int do_command(uint8_t cmd, const void *dout,
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size_t bytesout, void *din, size_t *bytesin)
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{
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size_t count;
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size_t max_in = MIN(*bytesin, SPI_FIFO_DEPTH);
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spi_write8(SPI_EXT_INDEX, SPI_TX_BYTE_COUNT);
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spi_write8(SPI_EXT_DATA, bytesout);
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spi_write8(SPI_EXT_INDEX, SPI_RX_BYTE_COUNT);
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spi_write8(SPI_EXT_DATA, max_in);
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spi_write8(SPI_CNTRL0, cmd);
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if (reset_internal_fifo_pointer())
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return -1;
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for (count = 0; count < bytesout; count++, dout++)
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spi_write8(SPI_CNTRL1, *(uint8_t *)dout);
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if (execute_command())
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return -1;
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if (reset_internal_fifo_pointer())
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return -1;
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for (count = 0; count < bytesout; count++)
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spi_read8(SPI_CNTRL1); /* skip the bytes we sent */
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for (count = 0; count < max_in; count++, din++)
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*(uint8_t *)din = spi_read8(SPI_CNTRL1);
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*bytesin -= max_in;
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return 0;
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}
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static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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size_t bytesout, void *din, size_t bytesin)
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{
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uint8_t cmd;
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/* First byte is cmd which cannot be sent through FIFO */
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cmd = *(uint8_t *)dout++;
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bytesout--;
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/*
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* Check if this is a write command attempting to transfer more bytes
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* than the controller can handle. Iterations for writes are not
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* supported here because each SPI write command needs to be preceded
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* and followed by other SPI commands, and this sequence is controlled
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* by the SPI chip driver.
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*/
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if (bytesout > SPI_FIFO_DEPTH) {
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printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI"
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" chip driver use spi_crop_chunk()?\n");
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return -1;
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}
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do {
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if (do_command(cmd, dout, bytesout, din, &bytesin))
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return -1;
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} while (bytesin);
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return 0;
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}
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int chipset_volatile_group_begin(const struct spi_flash *flash)
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{
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if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
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imc_sleep();
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return 0;
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}
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int chipset_volatile_group_end(const struct spi_flash *flash)
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{
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if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
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imc_wakeup();
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return 0;
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}
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static const struct spi_ctrlr spi_ctrlr = {
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.xfer = spi_ctrlr_xfer,
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.xfer_vector = spi_xfer_two_vectors,
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.max_xfer_size = SPI_FIFO_DEPTH,
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.deduct_cmd_len = true,
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};
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const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
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{
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.ctrlr = &spi_ctrlr,
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.bus_start = 0,
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.bus_end = 0,
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},
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};
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const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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