GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Doc/nb/intel/sandybridge: Fix up some typos and cosmetics 

Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2021-05-10 23:30:45 +02:00 committed by Patrick Georgi
parent 23e15b1223
commit 918e5352b7
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/northbridge/intel/sandybridge/index.md
View File

@ -4,6 +4,6 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid
## Topics ## Topics
- [Native Ram Initialization](nri.md) - [Native RAM Initialization](nri.md)
- [RAM initialization feature matrix](nri_features.md) - [RAM initialization feature matrix](nri_features.md)
- [ME Cleaner](me_cleaner.md) - [ME Cleaner](me_cleaner.md)

4
Documentation/northbridge/intel/sandybridge/nri.md
View File

@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties:
+---------+-------------------------------------------------------------------+------------+--------------+ +---------+-------------------------------------------------------------------+------------+--------------+
``` ```
## (Inoffical) register documentation ## (Unoffical) register documentation
- [Sandy Bridge - Register documentation](nri_registers.md) - [Sandy Bridge - Register documentation](nri_registers.md)
## Frequency selection ## Frequency selection
@ -83,7 +83,7 @@ in each DIMM's SPD.
> **Note:** This feature is available since coreboot 4.4 > **Note:** This feature is available since coreboot 4.4
### MRC cache ### MRC cache
The name *MRC cache* might be missleading as in case of *Native ram init* The name *MRC cache* might be misleading as in case of *Native RAM init*
there's no MRC, but for historical reasons it's still named *MRC cache*. there's no MRC, but for historical reasons it's still named *MRC cache*.
The MRC cache is part of flash memory that is writeable by coreboot. The MRC cache is part of flash memory that is writeable by coreboot.
At the end of the boot process coreboot will write the RAM training results to At the end of the boot process coreboot will write the RAM training results to

4
Documentation/northbridge/intel/sandybridge/nri_registers.md
View File

@ -1,9 +1,9 @@
# Inoffical Documentation of Intel MCHBAR register space. # Unofficial Documentation of Intel MCHBAR register space.
The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device. The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device.
This documentation is incomplete and might be incorrect. This documentation is incomplete and might be incorrect.
Please handle with care ! Please handle with care!
**MCHBAR + 0x4** **MCHBAR + 0x4**