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soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining 

We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters
for ADLRVP board.
Allowing this parameters to be filled by devicetree will allow
flexibility to update values as per board designs.
Note that both UPDs are applicable for both DDR and Lpddr memory types.

BUG=None
BRANCH=None
TEST=Build works and UPD values have been filled correctly

Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Maulik V Vaghela 2021-02-23 14:03:43 +05:30 committed by Werner Zeh
parent 4b97a13485
commit 91b2024bae
2 changed files with 12 additions and 0 deletions
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6
src/soc/intel/alderlake/include/soc/meminit.h
View File

@ -103,6 +103,12 @@ struct mb_cfg {
/* Board type */ /* Board type */
uint8_t UserBd; uint8_t UserBd;
/* Command Mirror */
uint8_t CmdMirror;
/* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */
uint8_t LpDdrDqDqsReTraining;
}; };
void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,

6
src/soc/intel/alderlake/meminit.c
View File

@ -226,6 +226,12 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
mem_cfg->UserBd = mb_cfg->UserBd; mem_cfg->UserBd = mb_cfg->UserBd;
set_rcomp_config(mem_cfg, mb_cfg); set_rcomp_config(mem_cfg, mb_cfg);
/* Fill command mirror for memory */
mem_cfg->CmdMirror = mb_cfg->CmdMirror;
/* Fill LpDdrrDqDqs Retraining for memory */
mem_cfg->LpDdrDqDqsReTraining = mb_cfg->LpDdrDqDqsReTraining;
switch (mb_cfg->type) { switch (mb_cfg->type) {
case MEM_TYPE_DDR4: case MEM_TYPE_DDR4:
case MEM_TYPE_DDR5: case MEM_TYPE_DDR5: