GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/lib: Capitalize ROM, RAM, NVRAM and CPU 

Change-Id: Id0871b0c2eb31e2d728180b44cc5b518b751add4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15985
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-07-30 15:51:13 +02:00 committed by Martin Roth
parent 7753731f0c
commit 91e0e3ccbe
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/lib/cbmem_console.c
View File

@ -41,7 +41,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p,
#ifdef __PRE_RAM__ #ifdef __PRE_RAM__
/* /*
* While running from ROM, before DRAM is initialized, some area in cache as * While running from ROM, before DRAM is initialized, some area in cache as
* ram space is used for the console buffer storage. The size and location of * RAM space is used for the console buffer storage. The size and location of
* the area are defined by the linker script with _(e)preram_cbmem_console. * the area are defined by the linker script with _(e)preram_cbmem_console.
*/ */

2
src/lib/selfboot.c
View File

@ -248,7 +248,7 @@ static int build_self_segment_list(
for (current_segment = first_segment;; ++current_segment) { for (current_segment = first_segment;; ++current_segment) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Loading segment from rom address 0x%p\n", "Loading segment from ROM address 0x%p\n",
current_segment); current_segment);
cbfs_decode_payload_segment(&segment, current_segment); cbfs_decode_payload_segment(&segment, current_segment);

2
src/lib/thread.c
View File

@ -43,7 +43,7 @@ static inline int thread_can_yield(const struct thread *t)
return (t != NULL && t->can_yield); return (t != NULL && t->can_yield);
} }
/* Assumes current cpu info can switch. */ /* Assumes current CPU info can switch. */
static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci) static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci)
{ {
return ci->thread; return ci->thread;

2
src/lib/tpm2_tlcl.c
View File

@ -301,7 +301,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size)
nvds_cmd.publicInfo.nvIndex = HR_NV_INDEX + space_index; nvds_cmd.publicInfo.nvIndex = HR_NV_INDEX + space_index;
nvds_cmd.publicInfo.nameAlg = TPM_ALG_SHA256; nvds_cmd.publicInfo.nameAlg = TPM_ALG_SHA256;
/* Attributes common for all NV ram spaces used by firmware. */ /* Attributes common for all NVRAM spaces used by firmware. */
nvds_cmd.publicInfo.attributes.TPMA_NV_PPWRITE = 1; nvds_cmd.publicInfo.attributes.TPMA_NV_PPWRITE = 1;
nvds_cmd.publicInfo.attributes.TPMA_NV_AUTHREAD = 1; nvds_cmd.publicInfo.attributes.TPMA_NV_AUTHREAD = 1;
nvds_cmd.publicInfo.attributes.TPMA_NV_PPREAD = 1; nvds_cmd.publicInfo.attributes.TPMA_NV_PPREAD = 1;