GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-02-24 00:51:11 +01:00
parent 972d9f2cce
commit 928a9c8f04
8 changed files with 18 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/amd/agesa/family14/fixme.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
@ -28,7 +29,7 @@ void amd_initcpuio(void)
PciData |= 1 << 7; // set NP (non-posted) bit
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */

3
src/cpu/amd/agesa/family15tn/fixme.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
@ -28,7 +29,7 @@ void amd_initcpuio(void)
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */

3
src/cpu/amd/agesa/family16kb/fixme.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
@ -28,7 +29,7 @@ void amd_initcpuio(void)
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */

3
src/cpu/amd/pi/00730F01/fixme.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
@ -32,7 +33,7 @@ void amd_initcpuio(void)
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
/* lowest NP address is HPET at FED00000 */
PciData = (0xFED00000 >> 8) | 3;
PciData = (HPET_BASE_ADDRESS >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */

6
src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl
View File

@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
/****************************************************************
* HPET
****************************************************************/
@ -8,7 +10,7 @@ Scope(\_SB) {
Device(HPET) {
Name(_HID, EISAID("PNP0103"))
Name(_UID, 0)
OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400)
OperationRegion(HPTM, SystemMemory, HPET_BASE_ADDRESS, 0x400)
Field(HPTM, DWordAcc, Lock, Preserve) {
VEND, 32,
PRD, 32,
@ -27,7 +29,7 @@ Scope(\_SB) {
}
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadOnly,
0xFED00000, // Address Base
HPET_BASE_ADDRESS, // Address Base
0x00000400, // Address Length
)
})

3
src/northbridge/intel/ironlake/northbridge.c
View File

@ -2,6 +2,7 @@
#include <console/console.h>
#include <acpi/acpi.h>
#include <arch/hpet.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <cpu/intel/model_2065x/model_2065x.h>
@ -48,7 +49,7 @@ static void add_fixed_resources(struct device *dev, int index)
0xff800000-0xffffffff ROM. */
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
resource->base = (resource_t) HPET_BASE_ADDRESS;
resource->size = (resource_t) 0x00100000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;

3
src/northbridge/intel/pineview/northbridge.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <cbmem.h>
#include <console/console.h>
#include <commonlib/bsd/helpers.h>
@ -26,7 +27,7 @@ static void add_fixed_resources(struct device *dev, int index)
struct resource *resource;
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
resource->base = (resource_t) HPET_BASE_ADDRESS;
resource->size = (resource_t) 0x00100000;
resource->flags = IORESOURCE_MEM
| IORESOURCE_RESERVE

3
src/soc/intel/xeon_sp/acpi/southcluster.asl
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/hpet.h>
#include <soc/iomap.h>
Name(_HID,EISAID("PNP0A08")) // PCIe
@ -120,7 +121,7 @@ Name (MCRS, ResourceTemplate() {
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed00000, 0xfedfffff, 0x00000000,
0x00000000, HPET_BASE_ADDRESS, 0xfedfffff, 0x00000000,
0x00100000,,, PCHR)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,