mb/google/brya/var/omnigul: Add variant specific devicetree
This variant was added without a devicetree, so add the board specific devicetree according to schematic_20230110. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
This commit is contained in:
Jamie Chen
Martin L Roth
parent
f700ddffb1
commit
92b60d1036
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@ -331,3 +331,4 @@ config BOARD_GOOGLE_OMNIGUL
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select SOC_INTEL_RAPTORLAKE
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select SOC_INTEL_RAPTORLAKE
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select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
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select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
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select DRIVERS_INTEL_ISH
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@ -1,6 +1,212 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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device domain 0 on
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register "sagv" = "SaGv_Enabled"
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end
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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# SOC Aux orientation override:
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# This is a bitfield that corresponds to up to 4 TCSS ports.
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# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
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# TcssAuxOri = 0101b
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# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
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# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
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# motherboard to USBC connector
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register "tcss_aux_ori" = "1"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
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register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3 Port 0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3 Port 2
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3 Port 3
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" # Type C port C0
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register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1
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register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" # Type C port C1
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register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable Port3
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# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
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# bypass rails implemented.
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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}"
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device domain 0 on
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/generic/alc1015
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register "hid" = ""RTL1019""
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register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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device generic 1 on end
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end
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end #I2C0
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end #I2C1
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device ref i2c3 on
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chip drivers/i2c/hid
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register "generic.hid" = ""GTCH7503""
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register "generic.desc" = ""G2TOUCH Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "50"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 40 on end
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end
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end #I2C3
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_14"
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register "detect" = "1"
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device i2c 15 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""SYNA0000""
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register "generic.cid" = ""ACPI0C50""
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register "generic.desc" = ""Synaptics Touchpad""
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register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "generic.wake" = "GPE0_DW2_14"
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register "generic.detect" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end #I2C5
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device ref pcie_rp8 off end
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device ref pcie_rp9 off end
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device ref ish on
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chip drivers/intel/ish
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register "add_acpi_dma_property" = "true"
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device generic 0 on end
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end
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end
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device ref ufs on end
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp2 off end
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device ref tcss_dma0 off end
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device ref tcss_dma1 off end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[2]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
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device ref usb3_port1 on end
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end
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end
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end
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end
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end
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end
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end
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