GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

northbridge/intel/e7505: Improve code formatting 

Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16632
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2016-09-17 21:05:10 +02:00 committed by Patrick Georgi
parent cf13950736
commit 9309552068
2 changed files with 44 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
src/northbridge/intel/e7505/debug.c
View File

@ -45,7 +45,7 @@ void dump_pci_device(unsigned dev)
for (i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
@ -72,18 +72,18 @@ void dump_pci_devices(void)
void dump_pci_devices_on_bus(unsigned busn)
{
pci_devfn_t dev;
for (dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
for (dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
void dump_spd_registers(const struct mem_controller *ctrl)
@ -113,18 +113,18 @@ void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel1[i];
if (device) {
int j;
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
for (j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
printk(BIOS_DEBUG, "\n%02x: ", j);
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
@ -133,24 +133,24 @@ void dump_spd_registers(const struct mem_controller *ctrl)
void dump_smbus_registers(void)
{
unsigned device;
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
if ( spd_read_byte(device, 0) < 0 ) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = spd_read_byte(device, j);
if (status < 0) {
for (j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
if ((j & 0xf) == 0)
}
if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
}
@ -159,27 +159,27 @@ void dump_io_resources(unsigned port)
int i;
printk(BIOS_DEBUG, "%04x:\n", port);
for (i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0)
for (i = 0; i < 256; i++) {
uint8_t val;
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
val = inb(port);
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
printk(BIOS_DEBUG, "\n");
}
if ((i & 0x0f) == 0x0f) {
printk(BIOS_DEBUG, "\n");
}
port++;
}
}
}
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
for (i=start;i<end;i++) {
for (i = start; i < end; i++) {
if ((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
printk(BIOS_DEBUG, "\n");
}
printk(BIOS_DEBUG, "\n");
}

4
src/northbridge/intel/e7505/raminit.c
View File

@ -1710,7 +1710,7 @@ static void sdram_enable(const struct mem_controller *ctrl)
/* And for good luck 6 more CBRs */
RAM_DEBUG_MESSAGE("Ram Enable 8\n");
int i;
for (i=0; i<8; i++)
for (i = 0; i < 8; i++)
do_ram_command(RAM_COMMAND_CBR, 0);
/* 9 mode register set */
@ -1823,7 +1823,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
/* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */
int i;
pci_write_config8(MCHDEV, PAM_0, 0x30);
for (i=1; i<=6; i++)
for (i = 1; i <= 6; i++)
pci_write_config8(MCHDEV, PAM_0 + i, 0x33);
/* Conservatively say each row has 64MB of ram, we will fix this up later