mb/google/sarien: Add Arcada variant
Add a variant of the Sarien board called Arcada. This is currently very similar to Sarien with differences in PCIe, USB, and GPIO usage. Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Duncan Laurie
Duncan Laurie
parent
558602ff40
commit
931a579a2e
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@ -30,6 +30,7 @@ config CHROMEOS
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config DEVICETREE
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string
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default "variants/arcada/devicetree.cb" if BOARD_GOOGLE_ARCADA
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default "variants/sarien/devicetree.cb" if BOARD_GOOGLE_SARIEN
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config DIMM_MAX
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@ -55,6 +56,7 @@ config TPM_TIS_ACPI_INTERRUPT
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config GBB_HWID
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string
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depends on CHROMEOS
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default "ARCADA TEST 3556" if BOARD_GOOGLE_ARCADA
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default "SARIEN TEST 2787" if BOARD_GOOGLE_SARIEN
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config MAINBOARD_DIR
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@ -63,10 +65,12 @@ config MAINBOARD_DIR
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config MAINBOARD_FAMILY
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string
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default "Google_Arcada" if BOARD_GOOGLE_ARCADA
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default "Google_Sarien" if BOARD_GOOGLE_SARIEN
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config MAINBOARD_PART_NUMBER
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string
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default "Arcada" if BOARD_GOOGLE_ARCADA
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default "Sarien" if BOARD_GOOGLE_SARIEN
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config MAINBOARD_VENDOR
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@ -79,6 +83,7 @@ config MAX_CPUS
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config VARIANT_DIR
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string
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default "arcada" if BOARD_GOOGLE_ARCADA
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default "sarien" if BOARD_GOOGLE_SARIEN
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config VBOOT
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@ -1,5 +1,9 @@
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comment "Sarien"
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config BOARD_GOOGLE_ARCADA
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bool "-> Arcada"
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select BOARD_GOOGLE_BASEBOARD_SARIEN
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config BOARD_GOOGLE_SARIEN
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bool "-> Sarien"
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select BOARD_GOOGLE_BASEBOARD_SARIEN
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@ -0,0 +1,19 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2018 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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verstage-y += gpio.c
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@ -0,0 +1,163 @@
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chip soc/intel/cannonlake
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "PMC_GPP_A"
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register "gpe0_dw1" = "PMC_GPP_C"
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register "gpe0_dw2" = "PMC_GPP_D"
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# FSP configuration
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register "SaGv" = "3"
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register "HeciEnabled" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "1"
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register "SataPortsDevSlp[2]" = "1"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "VmxEnable" = "1"
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register "speed_shift_enable" = "1"
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register "s0ix_enable" = "1"
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# Intel Common SoC Config
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
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register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 3
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register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 4
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_EMPTY"
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register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT)
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 3
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 4
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN)
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register "usb3_ports[4]" = "USB3_PORT_EMPTY"
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register "usb3_ports[5]" = "USB3_PORT_EMPTY"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
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#| I2C0 | Touchscreen |
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#| I2C1 | Touchpad |
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#| I2C4 | H1 TPM |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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},
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}"
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# PCIe port 9 for LAN
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register "PcieRpEnable[8]" = "1"
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register "PcieClkSrcUsage[0]" = "8"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe port 10 for M.2 2230 WLAN
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register "PcieRpEnable[9]" = "1"
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register "PcieClkSrcUsage[2]" = "9"
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register "PcieClkSrcClkReq[2]" = "2"
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# PCIe port 11 for card reader
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register "PcieRpEnable[10]" = "1"
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register "PcieClkSrcUsage[1]" = "10"
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register "PcieClkSrcClkReq[1]" = "1"
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# PCIe port 12 for M.2 3042
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register "PcieRpEnable[11]" = "1"
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register "PcieClkSrcUsage[3]" = "11"
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register "PcieClkSrcClkReq[3]" = "3"
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# PCIe port 13 for M.2 2280 SSD
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register "PcieRpEnable[12]" = "1"
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register "PcieClkSrcUsage[4]" = "12"
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register "PcieClkSrcClkReq[4]" = "4"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA Thermal device
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.5 off end # SDCard
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device pci 15.0 on end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""ACPI0C50""
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register "generic.desc" = ""Touchpad""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 19.0 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
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device i2c 50 on end
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end
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end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1 (USB)
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device pci 1c.1 off end # PCI Express Port 2 (USB)
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device pci 1c.2 off end # PCI Express Port 3 (USB)
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device pci 1c.3 off end # PCI Express Port 4 (USB)
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device pci 1c.4 off end # PCI Express Port 5 (USB)
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on end # PCI Express Port 9
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device pci 1d.1 on end # PCI Express Port 10
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device pci 1d.2 on end # PCI Express Port 11
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device pci 1d.3 on end # PCI Express Port 12
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device pci 1d.4 on end # PCI Express Port 13 (x4)
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on end # LPC/eSPI
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 on end # GbE
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end
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end
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@ -0,0 +1,263 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <variant/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_NC(GPP_A0, NONE),
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/* ESPI_IO0 */
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/* ESPI_IO1 */
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/* ESPI_IO2 */
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/* ESPI_IO3 */
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/* ESPI_CS# */
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/* SERIRQ */
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/* PIRQA# */ PAD_NC(GPP_A7, NONE),
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/* CLKRUN# */ PAD_NC(GPP_A8, NONE),
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/* ESPI_CLK */
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/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
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/* PME# */ PAD_NC(GPP_A11, NONE),
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/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
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/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
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/* ESPI_RESET# */
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/* SUSACK# */ PAD_NC(GPP_A15, NONE),
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/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
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/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
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/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
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/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
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/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
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/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
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/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
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/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
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/* CORE_VID0 */
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/* CORE_VID1 */
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/* VRALERT# */ PAD_NC(GPP_B2, NONE),
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/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,
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EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
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/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
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/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
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/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */
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/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
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/* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */
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/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
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/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE),
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/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
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/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
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/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
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/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
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/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */
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/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */
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/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K),
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/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */
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/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */
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/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K),
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/* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
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/* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
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/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
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/* UART0_TXD */ PAD_NC(GPP_C9, NONE),
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/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
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/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
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/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
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EDGE_SINGLE), /* SIO_EXT_WAKE# */
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/* UART1_TXD */ PAD_NC(GPP_C13, NONE),
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/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */
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/* UART1_CTS# */ PAD_NC(GPP_C15, NONE),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
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/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
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/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,
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EDGE_SINGLE, INVERT), /* TS_INT# */
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/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,
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EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
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/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
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/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */
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/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),
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/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */
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/* ISH_I2C0_ACC_SDA */
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/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* ISH_I2C0_ACC_SCL */
|
||||
/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE),
|
||||
/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),
|
||||
/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */
|
||||
/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),
|
||||
/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
|
||||
/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),
|
||||
/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
|
||||
/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
|
||||
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
|
||||
/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
|
||||
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
|
||||
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
|
||||
/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),
|
||||
/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),
|
||||
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */
|
||||
/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* WWAN_GPIO_PERST# */
|
||||
/* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,
|
||||
EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
|
||||
|
||||
/* SATAXPCIE0 */ PAD_NC(GPP_E0, NONE),
|
||||
/* M3042_PCIE#_SATA */
|
||||
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
|
||||
/* M2880_PCIE_SATA# */
|
||||
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
|
||||
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
|
||||
/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE),
|
||||
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
|
||||
/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
|
||||
/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
|
||||
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
|
||||
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
|
||||
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
|
||||
/* USB2_OC2# */ PAD_NC(GPP_E11, NONE),
|
||||
/* USB2_OC3# */ PAD_NC(GPP_E12, NONE),
|
||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
|
||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
|
||||
/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
|
||||
/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
|
||||
/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
|
||||
/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* CNV_PA_BLANKING */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */
|
||||
/* GPP_F1 */ PAD_NC(GPP_F1, NONE),
|
||||
/* GPP_F2 */ PAD_NC(GPP_F2, NONE),
|
||||
/* GPP_F3 */ PAD_NC(GPP_F3, NONE),
|
||||
/* CNV_BRI_DT */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* CNV_BRI_RSP */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
/* CNV_RGI_DT */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* CNV_RGI_RSP */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
|
||||
/* CNV_MFUART2_RXD */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */
|
||||
/* CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */
|
||||
/* GPP_F10 */ PAD_NC(GPP_F10, NONE),
|
||||
/* EMMC_CMD */ PAD_NC(GPP_F11, NONE),
|
||||
/* EMMC_DATA0 */ PAD_NC(GPP_F12, NONE),
|
||||
/* EMMC_DATA1 */ PAD_NC(GPP_F13, NONE),
|
||||
/* EMMC_DATA2 */ PAD_NC(GPP_F14, NONE),
|
||||
/* EMMC_DATA3 */ PAD_NC(GPP_F15, NONE),
|
||||
/* EMMC_DATA4 */ PAD_NC(GPP_F16, NONE),
|
||||
/* EMMC_DATA5 */ PAD_NC(GPP_F17, NONE),
|
||||
/* EMMC_DATA6 */ PAD_NC(GPP_F18, NONE),
|
||||
/* EMMC_DATA7 */ PAD_NC(GPP_F19, NONE),
|
||||
/* EMMC_RCLK */ PAD_NC(GPP_F20, NONE),
|
||||
/* EMMC_CLK */ PAD_NC(GPP_F21, NONE),
|
||||
/* EMMC_RESET# */ PAD_NC(GPP_F22, NONE),
|
||||
/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
|
||||
/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
|
||||
/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
|
||||
/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */
|
||||
/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
|
||||
/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
|
||||
/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
|
||||
/* SD_WP */ PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */
|
||||
|
||||
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
|
||||
/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */
|
||||
/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */
|
||||
/* I2S2_RXD */ PAD_NC(GPP_H3, NONE),
|
||||
/* I2C2_SDA */ PAD_NC(GPP_H4, NONE),
|
||||
/* I2C2_SCL */ PAD_NC(GPP_H5, NONE),
|
||||
/* I2C3_SDA */ PAD_NC(GPP_H6, NONE),
|
||||
/* I2C3_SCL */ PAD_NC(GPP_H7, NONE),
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
|
||||
/* I2C5_SDA */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* ISH_I2C2_SDA */
|
||||
/* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* ISH_I2C2_SCL */
|
||||
/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE),
|
||||
/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE),
|
||||
/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE),
|
||||
/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE),
|
||||
/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
|
||||
/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE),
|
||||
/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */
|
||||
/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),
|
||||
/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE),
|
||||
/* GPP_H21 */ PAD_NC(GPP_H21, NONE),
|
||||
/* GPP_H22 */ PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */
|
||||
/* GPP_H23 */ PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
|
||||
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
|
||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
|
||||
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
|
||||
/* GPD7 */ PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */
|
||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */
|
||||
/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */
|
||||
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */
|
||||
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
|
||||
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
|
||||
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
|
||||
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
|
||||
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
|
||||
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
|
||||
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
|
||||
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
|
||||
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
|
||||
CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Flash Write Protect */
|
||||
#define GPIO_PCH_WP GPP_E15
|
||||
|
||||
/* Recovery mode */
|
||||
#define GPIO_REC_MODE GPP_E8
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
struct cros_gpio;
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue