mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz

The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.

BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If59502aec7c3ab55864a518d626cde52aee18373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johnny Li 2020-07-23 13:37:30 +08:00 committed by Patrick Georgi
parent c8e4dcb569
commit 9399de9bb7
1 changed files with 43 additions and 0 deletions

View File

@ -1,5 +1,48 @@
chip soc/intel/tigerlake chip soc/intel/tigerlake
register "SaGv" = "SaGv_Disabled" register "SaGv" = "SaGv_Disabled"
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
#| I2C1 | Touchscreen |
#| I2C2 | WLAN, SAR0 |
#| I2C3 | Camera, SAR1 |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 163,
.scl_hcnt = 75,
.sda_hold = 36,
},
},
}"
device domain 0 on device domain 0 on
device pci 15.0 on device pci 15.0 on
chip drivers/i2c/generic chip drivers/i2c/generic