mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. Testing is successful if build completes successfully. TEST=Build for Galileo Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Lee Leahy
Martin Roth
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4af905ac95
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015-2016 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_INTEL_GALILEO
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select PLATFORM_USES_FSP1_1
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select SOC_INTEL_QUARK
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config MAINBOARD_DIR
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string
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default intel/galileo
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config MAINBOARD_PART_NUMBER
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string
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default "Galileo"
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config MAINBOARD_VENDOR
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string
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default "Intel"
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endif # BOARD_INTEL_QUARK
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2016 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config BOARD_INTEL_GALILEO
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bool "Galileo"
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015-2016 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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## Copyright (C) 2015-2016 Intel Corp.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/quark
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device domain 0 on
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# EDS Table 3
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device pci 00.0 on end # 8086 0958 - Host Bridge
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device pci 1f.0 on end # 8086 095e - Legacy Bridge
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end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <fsp/romstage.h>
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/* All FSP specific code goes in this block */
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void mainboard_romstage_entry(struct romstage_params *rp)
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{
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/* Call back into chipset code with platform values updated. */
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romstage_common(rp);
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}
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