cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCK
With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work, only powers of 2 are allowed as bootblock size. Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -18,6 +18,15 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
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#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
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#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
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#endif
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#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
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#else
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#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
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#endif
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.global bootblock_pre_c_entry
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.code32
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@ -148,13 +157,13 @@ addrsize_set_high:
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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andl $(~(XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x28)
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@ -18,6 +18,15 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
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#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
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#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
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#endif
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#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
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#else
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#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
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#endif
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.global bootblock_pre_c_entry
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.code32
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@ -136,13 +145,13 @@ addrsize_set_high:
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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andl $(~(XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x2e)
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@ -26,6 +26,15 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
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#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
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#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
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#endif
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#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
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#else
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#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
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#endif
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.global bootblock_pre_c_entry
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.code32
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@ -354,13 +363,13 @@ cache_rom:
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* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
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*/
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movl $_program, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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andl $(~(XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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rdmsr
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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fill_cache:
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