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cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCK 

With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the
size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work,
only powers of 2 are allowed as bootblock size.

Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-10-12 18:06:46 +02:00 committed by Patrick Georgi
parent 947916eb2d
commit 942ad6a137
3 changed files with 33 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/cpu/intel/car/core2/cache_as_ram.S
View File

@ -18,6 +18,15 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
.code32 .code32
@ -148,13 +157,13 @@ addrsize_set_high:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/ */
movl $_program, %eax movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax andl $(~(XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
post_code(0x28) post_code(0x28)

13
src/cpu/intel/car/p3/cache_as_ram.S
View File

@ -18,6 +18,15 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
.code32 .code32
@ -136,13 +145,13 @@ addrsize_set_high:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/ */
movl $_program, %eax movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax andl $(~(XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
post_code(0x2e) post_code(0x2e)

13
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -26,6 +26,15 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
.code32 .code32
@ -354,13 +363,13 @@ cache_rom:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/ */
movl $_program, %eax movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax andl $(~(XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
fill_cache: fill_cache: