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device/pci_device: Add generic subsystem programming logic 

This patch adds generic log to perform subsystem programming
based on header type.

Type 0: subsystem offset 0x2C
Type 2: subsystem offset 0x40
Type 1: Read CAP ID 0xD to know cap offset start, offset 4 to locate
subsystem vendor id.

Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2019-03-20 14:56:27 +05:30 committed by Patrick Georgi
parent 4a0f07166f
commit 9514d47d3c
2 changed files with 23 additions and 2 deletions
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24
src/device/pci_device.c
View File

@ -734,11 +734,31 @@ void pci_bus_reset(struct bus *bus)
void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, void pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device) unsigned int device)
{ {
uint8_t offset;
/* Header type */
switch (dev->hdr_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL:
offset = PCI_SUBSYSTEM_VENDOR_ID;
break;
case PCI_HEADER_TYPE_BRIDGE:
offset = pci_find_capability(dev, PCI_CAP_ID_SSVID);
if (!offset)
return;
offset += 4; /* Vendor ID at offset 4 */
break;
case PCI_HEADER_TYPE_CARDBUS:
offset = PCI_CB_SUBSYSTEM_VENDOR_ID;
break;
default:
return;
}
if (!vendor || !device) { if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config32(dev, offset,
pci_read_config32(dev, PCI_VENDOR_ID)); pci_read_config32(dev, PCI_VENDOR_ID));
} else { } else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config32(dev, offset,
((device & 0xffff) << 16) | (vendor & 0xffff)); ((device & 0xffff) << 16) | (vendor & 0xffff));
} }
} }

1
src/include/device/pci_def.h
View File

@ -198,6 +198,7 @@
#define PCI_CAP_ID_HT 0x08 /* Hypertransport */ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */
#define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
#define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */