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mb/google/dedede: Add console UART configuration 

Enable UART Port 2 as console UART and configure the concerned GPIOs.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-02-07 17:37:17 -07:00 committed by Patrick Georgi
parent 2a3cef29d8
commit 95ea799019
3 changed files with 12 additions and 2 deletions
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1
src/mainboard/google/dedede/Kconfig
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@ -6,6 +6,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2

4
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View File

@ -49,7 +49,7 @@ chip soc/intel/tigerlake
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
# Intel Common SoC Config
@ -91,7 +91,7 @@ chip soc/intel/tigerlake
device pci 17.0 off end # SATA
device pci 19.0 off end # I2C 4
device pci 19.1 off end # I2C 5
device pci 19.2 off end # UART 2
device pci 19.2 on end # UART 2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Root Port 1
device pci 1c.1 off end # PCI Express Root Port 2

9
src/mainboard/google/dedede/variants/baseboard/gpio.c
View File

@ -32,6 +32,15 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* C20 : UART_DBG_TX_AP_RX */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* C21 : UART_AP_TX_DBG_RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* C22 : UART2_RTS_N */
PAD_NC(GPP_C22, DN_20K),
/* C23 : UART2_CTS_N */
PAD_NC(GPP_C23, DN_20K),
};
/* Early pad configuration in bootblock */