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mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver 

This mainboard has three Marvel PHYs connected to the internal SOC GbE
controllers. The default LED status after HW reset of this PHYs shows a
different mode than what is needed. LED[2] is not connected on this
mainboard.

This patch sets the following LED status:
LED[0] - 7 = On - 1000 Mbps Link, Off - Else
LED[1] - 1 = On - Link, Blink - Activity, Off - No Link
LED[2] - not connected

TEST=Try different register values to verify LED feature.

Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2022-11-08 14:03:00 +01:00 committed by Martin L Roth
parent 1a97c89d7b
commit 969531b6d8
2 changed files with 40 additions and 3 deletions
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1
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVER_INTEL_I210 select DRIVER_INTEL_I210
select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
select EHL_TSN_DRIVER select EHL_TSN_DRIVER
select DRIVERS_ETH_PHY_M88E1512
config FMDFILE config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"

42
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
View File

@ -181,12 +181,48 @@ chip soc/intel/elkhartlake
device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0
device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 # Enable external Marvell PHY 88E1512
chip drivers/net/phy/m88e1512
register "configure_leds" = "true"
# LED[0]: On - 1000 Mbps Link, Off - Else
register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1"
device mdio 0 on # PHY address
ops m88e1512_ops
end
end
end
device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1
# Enable external Marvell PHY 88E1512
chip drivers/net/phy/m88e1512
register "configure_leds" = "true"
# LED[0]: On - 1000 Mbps Link, Off - Else
register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1"
device mdio 1 on # PHY address
ops m88e1512_ops
end
end
end
device pci 1e.0 on end # UART0 device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1 device pci 1e.1 on end # UART1
device pci 1e.4 on end # PCH Time-Sensitive Networking GbE device pci 1e.4 on # PCH Time-Sensitive Networking GbE
# Enable external Marvell PHY 88E1512
chip drivers/net/phy/m88e1512
register "configure_leds" = "true"
# LED[0]: On - 1000 Mbps Link, Off - Else
register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1"
device mdio 1 on # PHY address
ops m88e1512_ops
end
end
end
device pci 1f.0 on # eSPI Interface device pci 1f.0 on # eSPI Interface
chip drivers/pc80/tpm chip drivers/pc80/tpm