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amdfwtool: Change the name of macros for 'BHD' 

Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.

Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Zheng Bao 2021-06-11 15:54:40 +08:00 committed by Felix Held
parent 22ef1439dd
commit 96a3371a72
4 changed files with 14 additions and 14 deletions
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4
src/soc/amd/common/psp_verstage/include/psp_verstage.h
View File

@ -11,7 +11,7 @@
#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
#define PSP_COOKIE 0x50535024 /* 'PSP$' */
#define BDT1_COOKIE 0x44484224 /* 'DHB$ */
#define BHD_COOKIE 0x44484224 /* 'DHB$ */
#define PSP_VBOOT_ERROR_SUBCODE 0x0D5D0000
@ -31,7 +31,7 @@
#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3
#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4
#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5
#define POSTCODE_BDT1_COOKIE_MISMATCH_ERROR 0xC6
#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6
#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7
#define POSTCODE_FMAP_REGION_MISSING 0xC8
#define POSTCODE_AMD_FW_MISSING 0xC9

4
src/soc/amd/common/psp_verstage/psp_verstage.c
View File

@ -110,9 +110,9 @@ static uint32_t update_boot_region(struct vb2_context *ctx)
printk(BIOS_ERR, "PSP Directory address is not correct.\n");
return POSTCODE_PSP_COOKIE_MISMATCH_ERROR;
}
if (*bios_dir_in_spi != BDT1_COOKIE) {
if (*bios_dir_in_spi != BHD_COOKIE) {
printk(BIOS_ERR, "BIOS Directory address is not correct.\n");
return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR;
return POSTCODE_BHD_COOKIE_MISMATCH_ERROR;
}
/* EFS2 uses relative address and PSP isn't happy with that */

16
util/amdfwtool/amdfwtool.c
View File

@ -492,8 +492,8 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, co
+ sizeof(dir->header.num_entries)
+ sizeof(dir->header.additional_info));
break;
case BDT1_COOKIE:
case BDT2_COOKIE:
case BHD_COOKIE:
case BHDL2_COOKIE:
table_size = ctx->current - ctx->current_table;
if ((table_size % TABLE_ALIGNMENT) != 0) {
fprintf(stderr, "The BIOS table size should be 4K aligned\n");
@ -1005,7 +1005,7 @@ static void integrate_bios_firmwares(context *ctx,
*/
if (!cb_config->multi_level)
level = BDT_BOTH;
else if (cookie == BDT2_COOKIE)
else if (cookie == BHDL2_COOKIE)
level = BDT_LVL2;
else if (biosdir2)
level = BDT_LVL1;
@ -1926,12 +1926,12 @@ int main(int argc, char **argv)
biosdir2 = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir2, NULL,
amd_bios_table, BDT2_COOKIE, &cb_config);
amd_bios_table, BHDL2_COOKIE, &cb_config);
if (cb_config.recovery_ab) {
if (pspdir2_b != NULL) {
biosdir2_b = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir2_b, NULL,
amd_bios_table, BDT2_COOKIE, &cb_config);
amd_bios_table, BHDL2_COOKIE, &cb_config);
}
add_psp_firmware_entry(&ctx, pspdir2, biosdir2,
AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT);
@ -1941,13 +1941,13 @@ int main(int argc, char **argv)
} else {
biosdir = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir, biosdir2,
amd_bios_table, BDT1_COOKIE, &cb_config);
amd_bios_table, BHD_COOKIE, &cb_config);
}
} else {
/* flat: BDT1 cookie and no pointer to 2nd table */
/* flat: BHD1 cookie and no pointer to 2nd table */
biosdir = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir, NULL,
amd_bios_table, BDT1_COOKIE, &cb_config);
amd_bios_table, BHD_COOKIE, &cb_config);
}
switch (soc_id) {
case PLATFORM_RENOIR:

4
util/amdfwtool/amdfwtool.h
View File

@ -252,8 +252,8 @@ typedef struct _ish_directory_table {
#define PSP_COOKIE 0x50535024 /* 'PSP$' */
#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
#define PSP2_COOKIE 0x50535032 /* 'PSP2' */
#define BDT1_COOKIE 0x44484224 /* 'DHB$ */
#define BDT2_COOKIE 0x324c4224 /* '2LB$ */
#define BHD_COOKIE 0x44484224 /* 'DHB$ */
#define BHDL2_COOKIE 0x324c4224 /* '2LB$ */
#define PSP_LVL1 (1 << 0)
#define PSP_LVL2 (1 << 1)