soc/intel/skylake: move heci_init() from bootblock to romstage

Aligns with all other soc/intel/common platforms calling heci_init().

Test: build/boot Purism Librem 13v2

Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/skylake/bootblock/pch.c

@@ -2,7 +2,6 @@
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <intelblocks/cse.h>
 #include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
@@ -141,8 +140,5 @@ void bootblock_pch_init(void)
 
 	enable_rtc_upper_bank();
 
-	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
-
 	gspi_early_bar_init();
 }

src/soc/intel/skylake/romstage/romstage.c

@@ -4,6 +4,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/util.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/smbus.h>
 #include <memory_info.h>
@@ -127,6 +128,8 @@ void mainboard_romstage_entry(void)
 	systemagent_early_init();
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
+	/* initialize Heci interface */
+	heci_init(HECI1_BASE_ADDRESS);
 	ps = pmc_get_power_state();
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);