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soc/intel/xeon_sp: use VGA_MMIO_* defines from arch/vga.h 

Now that we have x86 architecture specific VGA_MMIO_* defines in
arch/vga.h, use those instead of having SoC-specific defines for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77b914d563bdc83e7fad7d7fccd5cf7777cb4918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-06-05 19:30:23 +02:00
parent 8193eabd8d
commit 97439ecc01
5 changed files with 11 additions and 14 deletions
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6
src/soc/intel/xeon_sp/cpx/soc_acpi.c
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@ -2,6 +2,7 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <arch/vga.h>
#include <assert.h> #include <assert.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <device/mmio.h> #include <device/mmio.h>
@ -87,9 +88,8 @@ void uncore_inject_dsdt(const struct device *device)
/* additional mem32 resources on socket 0 bus 0 */ /* additional mem32 resources on socket 0 bus 0 */
if (stack == 0) { if (stack == 0) {
acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
(VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
VGA_BASE_SIZE);
acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
SPI_BASE_SIZE); SPI_BASE_SIZE);

4
src/soc/intel/xeon_sp/include/soc/iomap.h
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@ -22,10 +22,6 @@
#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS #define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS
#define ACPI_BASE_SIZE 0x100 #define ACPI_BASE_SIZE 0x100
/* Video RAM */
#define VGA_BASE_ADDRESS 0xa0000
#define VGA_BASE_SIZE 0x20000
#define HECI1_BASE_ADDRESS 0xfed1a000 #define HECI1_BASE_ADDRESS 0xfed1a000
#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS #define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS

6
src/soc/intel/xeon_sp/skx/soc_acpi.c
View File

@ -2,6 +2,7 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <arch/vga.h>
#include <assert.h> #include <assert.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <device/mmio.h> #include <device/mmio.h>
@ -121,9 +122,8 @@ void uncore_inject_dsdt(const struct device *device)
// additional mem32 resources on socket 0 bus 0 // additional mem32 resources on socket 0 bus 0
if (socket == 0 && stack == 0) { if (socket == 0 && stack == 0) {
acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
(VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
VGA_BASE_SIZE);
acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
SPI_BASE_SIZE); SPI_BASE_SIZE);

6
src/soc/intel/xeon_sp/spr/soc_acpi.c
View File

@ -2,6 +2,7 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <arch/vga.h>
#include <assert.h> #include <assert.h>
#include <cbmem.h> #include <cbmem.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
@ -131,9 +132,8 @@ static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const ST
/* Additional Mem32 resources on socket 0 bus 0 */ /* Additional Mem32 resources on socket 0 bus 0 */
if (socket == 0 && stack == 0) { if (socket == 0 && stack == 0) {
acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
(VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
VGA_BASE_SIZE);
acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
SPI_BASE_SIZE); SPI_BASE_SIZE);

3
src/soc/intel/xeon_sp/uncore.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <arch/vga.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/lapic_def.h> #include <cpu/x86/lapic_def.h>
@ -306,7 +307,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
* 0xa0000 - 0xbffff: legacy VGA * 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM * 0xc0000 - 0xfffff: RAM
*/ */
res = mmio_range(dev, index++, VGA_BASE_ADDRESS, VGA_BASE_SIZE); res = mmio_range(dev, index++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
LOG_RESOURCE("legacy_mmio", dev, res); LOG_RESOURCE("legacy_mmio", dev, res);
res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); res = reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);