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smaug: Update PMIC settings 

Update PMIC settings as per table provided by hardware eng team.

Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec
Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283543
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2015-07-06 13:40:50 -07:00 committed by Patrick Georgi
parent dc197619cd
commit 9761a7a295
2 changed files with 24 additions and 16 deletions
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37
src/mainboard/google/smaug/pmic.c
View File

@ -84,29 +84,34 @@ void pmic_init(unsigned bus)
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1);
/* MAX77620: Set SD0 to 1.0V - VDD_CORE */
pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1);
pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1);
/* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */
pmic_write_reg_77620(bus, MAX77620_GPIO1_REG, 0x09, 1);
/* MAX77620: GPIO 0,1,2,5,6,7 = GPIO, 3,4 = alt mode */
pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x18, 1);
/* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x1c, 1);
/* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */
/* MAX77620: Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125V */
pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1);
/* Max77621 VREG for CPU needs to be set to 0.85V as per SysEng */
/* MAX77621: Set VOUT_REG to 1.0V - CPU VREG */
pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xBF, 1);
/* Max77621 CPU VREG, register 0, 0.85V = 0x27(0.60625 + (39*6.25mV)) */
pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0x27, 1);
pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xa7, 1);
/* MAX77621: Set VOUT_DVC_REG to 1.0V - CPU VREG DVC */
pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xBF, 1);
/* Max77621 CPU VREG DVC, register 1, 0.85V = 0x27 */
pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0x27, 1);
pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xa7, 1);
/* MAX77621: Set CONTROL1 to 0x38 */
pmic_write_reg_77621(bus, MAX77621_CONTROL1_REG, 0x38, 1);
/* MAX77621: Set CONTROL2 to 0xD2 */
pmic_write_reg_77621(bus, MAX77621_CONTROL2_REG, 0xD2, 1);
/* MAX77620: Setup/Enable GPIO5 - EN_VDD_CPU */
pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1);
/* Required delay of 2msec */
udelay(2000);
printk(BIOS_DEBUG, "PMIC init done\n");
}

3
src/mainboard/google/smaug/pmic.h
View File

@ -25,6 +25,7 @@
#define MAX77620_SD1_REG 0x17
#define MAX77620_SD2_REG 0x18
#define MAX77620_SD3_REG 0x19
#define MAX77620_VDVSSD0_REG 0x1B
#define MAX77620_CNFG2SD_REG 0x22
#define MAX77620_CNFG1_L0_REG 0x23
@ -71,6 +72,8 @@
#define MAX77621_VOUT_REG 0x00
#define MAX77621_VOUT_DVC_REG 0x01
#define MAX77621_CONTROL1_REG 0x02
#define MAX77621_CONTROL2_REG 0x03
void pmic_init(unsigned bus);
void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val,